xr16v554 Exar Corporation, xr16v554 Datasheet
xr16v554
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xr16v554 Summary of contents
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... The XR16V554IV (64-pin) offers three state interrupt output while the XR16V554DIV provides continuous interrupt output. The XR16V554 is compatible with the industry standard ST16C554 XR16V554 B D IGURE LOCK IAGRAM ...
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... DTRC# CTSB CTSC# DSRB DSRC# XR16V554/554D 64-pin TQFP Intel Mode Only 2 REV. 1.0.2 64- LQFP P ODE AND PIN ACKAGES 60 DSRD# 59 CTSD# 58 DTRD# 57 GND 56 RTSD# 55 N.C. XR16V554 54 N.C. 68-pin PLCC 53 TXD 52 N.C. Motorola Mode 51 TXC N.C. 48 RTSC# 47 VCC 46 DTRC# 45 CTSC# 44 DSRC# 48 DSRD# 47 CTSD# 46 DTRD# ...
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... CSC# INTB 10 26 INTC RTSB# 11 CTSB# 25 RTSC# 12 XR16 V 554 80 - pin LQFP Intel Mode Only 3 XR16V554/554D ACKAGE 36 RXD 35 CTSD# GND 34 33 RTSD# 32 INTD XR16V554 CSD# 31 48-pin QFN Motorola Mode 30 TXD 29 IOR# 28 TXC 27 CSC# 26 INTC 25 RTSC CDC# 58 RIC# 57 RXC 56 GND 55 TXRDY# ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO ORDERING INFORMATION P N ART UMBER XR16V554IJ XR16V554IV XR16V554DIV XR16V554IL XR16V554IV80 PIN DESCRIPTIONS Pin Description 48-QFN 64-LQFP 68-PLCC N AME DATA BUS INTERFACE ...
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... Transmitter Ready (active low). This output is a logi- cally ANDed status of TXRDY# A-D. See output is unused, leave it unconnected Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A-D. See put is unused, leave it unconnected. 5 XR16V554/554D D ESCRIPTION Table 5. If this Table 5. If this out- ...
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... For the 64 pin packages, this pin is bonded to VCC internally in the XR16V554D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the XR16V554 and there- fore requires setting MCR bit-3 for enabling the inter- rupt output pins. ...
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... GND on the PCB. The thermal pad size on the PCB should be the approx- imate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. 7 XR16V554/554D D ESCRIPTION ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO Pin Description 48-QFN 64-LQFP 68-PLCC N AME N. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 80-LQFP T YPE 10, 20, No Connection. These pins are not used in either the 21, 30, Intel or Motorola bus modes. ...
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... The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has 16 bytes of transmit and receive FIFOs, programmable baud rate generator and data rate Mbps at 3.3 V. The XR16V554 can operate from 2.25 to 3.6 volts. The V554 is fabricated with an advanced CMOS process. ...
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... UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown XR16V554 T I IGURE YPICAL NTEL ...
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... Channel A selected Channel B selected Channel C selected Channel D selected Channels A-D selected See Table A HANNEL ELECT UNCTION X X UART de-selected 0 0 Channel A selected 0 1 Channel B selected 1 0 Channel C selected 1 1 Channel D selected 11 XR16V554/554D Table 1. ODE ODE ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 2.4 Channels A-D Internal Registers Each UART channel in the V554 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers ...
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... HIGH = at least 1 byte in FIFO HIGH = FIFO is full “Section 2.8, Programmable Baud Rate Generator” on page 21. R=300K to 400K 14.7456 XTAL1 XTAL2 MHz C1 C2 22-47pF 22-47pF Table 6 shows the standard data rates available Table 6. 13 XR16V554/554D C A-D ODE FOR HANNELS ) NABLED FCR (DMA ODE NABLED ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO IGURE AUD ATE ENERATOR Crystal XTAL1 Osc / XTAL2 Buffer ABLE YPICAL DATA RATES WITH A O Data Rate D UTPUT IVISOR FOR MCR Bit-7=0 Clock (Decimal) 400 2304 2400 384 4800 192 9600 96 19 ...
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... THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 M Transmit Shift Register (TSR FIFO AND LOW ONTROL ODE Transmit THR Interrupt (ISR bit-1) FIFO When it becomes empty. FIFO is Enabled by FCR Bit-0=1 Transmit Data Shift Register ( TSR ) 15 XR16V554/554D TXNOFIFO1 TXFIFO1 ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 2.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X clock rate ...
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... Interrupt (IS R bit-2) program m ed for D ata FIFO Trigger=8 desired FIFO trigger level. FIFO is Enabled bit-0=1 D ata fills to Asking for stopping data w hen data fills above the flow 14 control trigger level to suspend rem ote transm itter. R eceive D ata 17 XR16V554/554D R eceive D ata C haracters R X FIFO 1 ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 2.11 Internal Loopback The V554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
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... The complete register set is shown UART I R ABLE NTERNAL EGISTERS R R EGISTER EAD 16C550 C R OMPATIBLE EGISTERS Read-only Write-only Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Read/Write 19 XR16V554/554D /W C RITE OMMENTS LCR[ LCR[ LCR ≠ 0xBF LCR[ LCR[ ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO T ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/ ISR RD FIFOs Enabled FCR WR RX FIFO Trigger LCR RD/WR Divisor Enable MCR RD/ LSR ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16V554 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 4.4 Interrupt Status Register (ISR) The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued serviced next ...
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... FIFO crosses the trigger level. T ABLE FCR B 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO Table 10 10: R FIFO T L ECEIVE RIGGER EVEL -7 FCR ECEIVE RIGGER XR16V554/554D shows the complete selections. S ELECTION L EVEL ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register ...
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... In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal. 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO T 11: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, HIGH 1 1 Forced parity to space, LOW 25 XR16V554/554D ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO MCR[3]: INT Output Enable Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is also used to control the OP2# signal during internal loopback mode. INTSEL pin must be LOW during 68 mode. • ...
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... MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 27 ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO MSR[4]: CTS Input Status A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used ...
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... Bits 7-0 = 0x00 Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF RESET STATE HIGH HIGH HIGH HIGH LOW XR16V554 = Three-State Condition (INTSEL = LOW) XR16V554 = LOW (INTSEL = HIGH) XR16V554D = LOW HIGH (INTSEL = LOW) 29 XR16V554/554D ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-QFN) Thermal Resistance (64-LQFP) Thermal Resistance (68-PLCC) Thermal Resistance (80-LQFP) ELECTRICAL CHARACTERISTICS ...
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... RSI 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 3.6V LOAD WHERE APPLICABLE 2.5V ± 10 XR16V554/554D L L IMITS IMITS 3.3V ± 10% U NIT MHz 50 64 MHz ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay From Stop To Set Interrupt SSI T Delay From IOR# To Reset Interrupt RRI T Delay From Start To Interrupt SI T Delay From Initial INT Reset To Transmit Start ...
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... RDV Valid Data 33 XR16V554/554D Valid Address T ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO F 15 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# T RDA D0- A-D US RITE IMING FOR HANNELS ...
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... T [N -FIFO M ] IMING ON ODE FOR Stop D0:D7 Bit T T SSR SSR 1 Byte 1 Byte in RHR in RHR T T SSR SSR Active Active Data Data Ready Ready XR16V554/554D A-D Valid Address Valid Data 68Write C A-D HANNELS D0:D7 T SSR 1 Byte in RHR T SSR Active Data Ready T RR RXNFM ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO F 19 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. ...
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... SSI T SSR T [FIFO M , DMA M IMING ODE Stop Bit T D0:D7 S D0:D7 S D0: below trigger level T WRI 37 XR16V554/554D ] C A-D FOR HANNELS D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXFIFODMA A-D ODE ISABLED FOR HANNELS Last Data Byte ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO F 23 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0:D7 S D0:D7 T (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data into FIFO) *INT cleared when the ISR is read or when TX FIFO fills up to trigger level. ...
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... Note: The actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm. The lead may be half-etched terminal. INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.270 0.281 6.85 0.201 0.209 5.10 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.012 0.020 0.30 0.008 - 0.20 39 XR16V554/554D MAX 1.00 0.05 0.25 7.15 5.30 0.30 0.50 - ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 64 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) A Seating Plane Note: The control dimension is the millimeter column SYMBOL α INCHES MILLIMETERS MIN MAX MIN 0 ...
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... BSC 1.27 BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 41 XR16V554/554D C Seating Plane 45 ° MAX 5.08 3.30 --- 0.53 0.81 0.32 25.27 24.33 23.62 1.42 1.22 1.14 ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 80 LEAD PLASTIC QUAD FLAT PACK ( LQFP, 1.4 mm Form) Note: The control dimension is the millimeter column SYMBOL α INCHES MILLIMETERS MIN MAX MIN 0.055 0.063 1.40 0.002 0.006 0.05 0.053 0.057 1.35 0.007 ...
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... Copyright 2007 EXAR Corporation Datasheet September 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO D ESCRIPTION NOTICE 43 XR16V554/554D ...
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... REV. 1.0.2 GENERAL DESCRIPTION................................................................................................ 1 F .................................................................................................................................................... 1 EATURES A .............................................................................................................................................. 1 PPLICATIONS F 1. XR16V554 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT IGURE IN UT SSIGNMENT OR PIN DESCRIPTIONS ......................................................................................................... 4 ............................................................................................................................... 4 ORDERING INFORMATION 1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9 2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10 2.1 CPU INTERFACE .............................................................................................................................................. XR16V554 IGURE YPICAL NTEL 2 ...
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... XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 28 4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 28 T 13: UART RESET CONDITIONS FOR CHANNELS A-D .................................................................................................. 29 ABLE ABSOLUTE MAXIMUM RATINGS.................................................................................. 30 TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 30 ELECTRICAL CHARACTERISTICS ............................................................................... 30 ...