xr16l2550im Exar Corporation, xr16l2550im Datasheet
xr16l2550im
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xr16l2550im Summary of contents
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MAY 2007 GENERAL DESCRIPTION 1 The XR16L2550 (L2550 dual universal asynchronous receiver and transmitter (UART). The XR16L2550 is an improved ST16C2550 UART with lower operating voltages and 5 volt tolerant inputs. The L2550 provides enhanced UART functions with ...
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... D7 9 RXB 10 RXA 11 XR16L2550 TXRDYB# 12 44-pin PLCC TXA 13 TXB 14 OP2B# 15 CSA# 16 CSB# 17 ORDERING INFORMATION ART UMBER XR16L2550IL 32-Lead QFN XR16L2550IJ 44-Lead PLCC XR16L2550IM 48-Lead TQFP 36 RESET 35 DTRB# 34 DTRA# 33 RTSA# 32 OP2A# 31 RXRDYA# 30 INTA 29 INTB RXB ...
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REV. 1.1.2 PIN DESCRIPTIONS Pin Description 32-QFN 44-PLCC 48-TQFP N AME DATA BUS INTERFACE ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO Pin Description 32-QFN 44-PLCC 48-TQFP N AME TXRDYB RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 5 13 RXA 4 11 RTSA ...
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REV. 1.1.2 Pin Description 32-QFN 44-PLCC 48-TQFP N AME RTSB CTSB DTRB DSRB CDB RIB OP2B ANCILLARY SIGNALS XTAL1 10 ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16L2550 (L2550) provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. necessary for converting the serial data stream into parallel ...
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REV. 1.1.2 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The L2550 data interface supports the Intel compatible types ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in Table 1. CSA 2.6 Channel A and B Internal Registers Each UART ...
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REV. 1.1 INTA ABLE FCR (FIFO D ISABLED INTA/B Pin byte in THR 1 = THR empty T 4: INTA ABLE FCR (FIFO D ISABLED ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.10 Programmable Baud Rate Generator A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a ...
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REV. 1.1.2 The L2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock 16 by ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO IGURE RANSMITTER Data Byte 16X Clock Transmit Shift Register (TSR) 2.11.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit ...
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REV. 1.1.2 when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7- 4.6 character times. The RHR interrupt is enabled by IER bit-0. 2.12.1 Receive Holding Register (RHR) ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume ...
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REV. 1.1.2 F 11. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the L2550 will halt ...
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REV. 1.1.2 2.17 Infrared Mode The L2550 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/ bit wide ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.18 Sleep Mode with Auto Wake-Up The L2550 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of ...
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REV. 1.1.2 2.19 Internal Loopback The L2550 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 13 shows ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the L2550 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the ...
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REV. 1.1 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO T 8: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS Enable XON1 ...
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REV. 1.1.2 IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. • ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 Interrupt Generation: • LSR is by ...
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REV. 1.1.2 ISR[0]: Interrupt Status • Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • Logic interrupt pending (default condition). ISR[3:1]: Interrupt ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive ...
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REV. 1.1.2 LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. • Logic 0 = ODD Parity is generated by ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO MCR[1]: RTS# Output The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. • Logic 0 = Force ...
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REV. 1.1.2 LSR[1]: Receiver Overrun Flag • Logic overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO MSR[0]: Delta CTS# Input Flag • Logic change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A ...
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REV. 1.1.2 4.13 Device Revision Register (DREV) - Read Only This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00. 4.14 Enhanced Feature Register ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 ...
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REV. 1.1.2 T 13: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS XON1 XON2 XOFF1 XOFF2 I/O SIGNALS RXRDY# TXRDY# LOW VOLTAGE DUART WITH 16-BYTE FIFO RESET STATE DLM Bits 7-0 = 0xXX DLL Bits 7-0 = 0xXX ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (44-PLCC) Thermal Resistance (32-QFN) ELECTRICAL CHARACTERISTICS DC ...
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REV. 1.1.2 AC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED LOAD WHERE APPLICABLE S P YMBOL ARAMETER - Crystal Frequency CLK External Clock Low/High Time OSC External Clock Frequency T Address Setup Time AS T Address ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED LOAD WHERE APPLICABLE S P YMBOL ARAMETER T Reset Pulse Width RST N Baud Rate Divisor Bclk Baud Clock F 14. ...
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REV. 1.1 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE IMING A0-A2 Valid Address T AS ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO F 18 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX ...
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REV. 1.1 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO) F ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO F 22 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* T WRI Data in TX FIFO TXRDY# T ...
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REV. 1.1.2 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL α LOW VOLTAGE DUART WITH 16-BYTE ...
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XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL ...
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REV. 1.1.2 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL LOW VOLTAGE DUART WITH 16-BYTE FIFO ) mm INCHES MILLIMETERS ...
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... Updated QFN package dimensions drawing to show minimum "k" parameter. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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LOW VOLTAGE DUART WITH 16-BYTE FIFO GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................... 1 PPLICATIONS F ..................................................................................................................................................... 1 EATURES F 1. XR16L2550 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ 2 ORDERING ...
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XR16L2550 REV. 1.1.2 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 24 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 25 T 10: R FIFO T L ABLE ECEIVE ...