71m6534h-igt Maxim Integrated Products, Inc., 71m6534h-igt Datasheet
71m6534h-igt
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71m6534h-igt Summary of contents
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... KB shared RAM and 128 KB (71M6533/H, 71M6534) or 256 KB (71M6534H) Flash which may be programmed in the field with new code and/or data during meter operation. Higher processing and sampling rates and larger memory offer a po- werful metering platform for commercial and industrial meters with up to class 0 ...
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Data Sheet 1 Hardware Description ......................................................................................................................... 9 1.1 Hardware Overview .................................................................................................................... 9 1.2 Analog Front End (AFE) .......................................................................................................... 10 1.2.1 Signal Input Pins ............................................................................................................ 10 1.2.2 Input Multiplexer............................................................................................................. 10 1.2.3 A/D Converter (ADC) ..................................................................................................... 11 1.2.4 FIR Filter ........................................................................................................................ ...
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... Wake on PB ................................................................................................................... 63 2.5.2 Wake on Timer............................................................................................................... 63 2.6 Data Flow .................................................................................................................................. 64 2.7 CE/MPU Communication ......................................................................................................... 64 3 Application Information .................................................................................................................... 65 3.1 Connection of Sensors (CT, Resistive Shunt) ...................................................................... 65 3.2 Distinction between 71M6533/71M6534 and 71M6533H/71M6534H Parts .......................... 65 3.3 Connecting 5 V Devices .......................................................................................................... 66 3.4 Temperature Measurement ..................................................................................................... 66 3.5 Temperature Compensation ................................................................................................... 66 3.5.1 Temperature Coefficients .............................................................................................. 66 3.5.2 Temperature Compensation for VREF .......................................................................... 67 3.5.3 System Temperature Compensation ............................................................................. 67 3.5.4 Temperature Compensation for the RTC ...................................................................... 67 3 ...
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... Package Outline Drawings .................................................................................................... 113 5.7.1 71M6533 (100 Pin LQFP) ............................................................................................ 113 5.7.2 71M6534/6534H (120 Pin LQFP) ................................................................................ 114 5.8 Pinout ...................................................................................................................................... 115 5.8.1 71M6533/71M6533H Pinout (100 Pin LQFP) .............................................................. 115 5.8.2 71M6534/71M6534H Pinout (120 Pin LQFP) .............................................................. 116 5.9 Pin Descriptions ..................................................................................................................... 117 5.9.1 Power and Ground Pins ............................................................................................... 117 5.9.2 Analog Pins .................................................................................................................. 117 5.9.3 Digital Pins ................................................................................................................... 118 5 ...
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... Figure 47: Typical Wh Accuracy (0. 200 A, 240 V, Room Temperature), Various Load Angles (Differential Mode, CTs) ..................................................................................................................... 112 Figure 48: 71M6533/6533H 100-pin LQFP Package Outline ................................................................... 113 Figure 49: 71M6534/6534H 120-pin LQFP Package Outline ................................................................... 114 Figure 50: Pinout for 71M6533/71M6533H LQFP-100 Package .............................................................. 115 Figure 51: Pinout for 71M6534/71M6534H LQFP-120 Package .............................................................. 116 v1.1 © 2007-2009 TERIDIAN Semiconductor Corporation 71M6533/71M6534 Data Sheet 5 ...
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Data Sheet Tables Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV = 7) ................... 11 Table 2: ADC Resolution ............................................................................................................................. 11 Table 3: ADC RAM Locations ..................................................................................................................... 12 Table 4: XRAM Locations for ADC Results ...
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FDS_6533_6534_004 Table 56: CE Energy Measurement Variables............................................................................................ 96 Table 57: Other Transfer Variables ............................................................................................................. 96 Table 58: CE Temperature Registers ......................................................................................................... 97 Table 59: CE Pulse Generation Parameters ............................................................................................... 98 Table 60: CE Parameters for Noise Suppression and Code Version ...
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Data Sheet VREF IAP IAN VA VBIAS IBP MUXP IBN VB VADC ICP ICN VC VREF VREF_CAL EQU VREF_DIS MUX_AL MUX_DIV VBAT TEMP 2.5V_NV MCK RTCLK (32KHz) PLL OSC XIN MPU_DIV (32KHz) CKOUT_E ...
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FDS_6533_6534_004 1 Hardware Description 1.1 Hardware Overview The Teridian 71M6533 and 71M6534 single-chip energy meter integrate all primary functional blocks re- quired to implement a solid-state electricity meter. Included on the chip are: An analog front end (AFE) An Independent ...
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Data Sheet 1.2 Analog Front End (AFE) The AFE of the 71M6533/71M6534 consists of an input multiplexer, a delta-sigma A/D converter and a voltage reference. 1.2.1 Signal Input Pins All analog signal input pins are sensitive to voltage. The ...
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FDS_6533_6534_004 cal assignment of values for the SLOTn_SEL and SLOTn_ALTSEL registers assuming seven time slots (MUX_DIV = 7) for the processing of three voltage and current phases plus an additional neutral current. The correlation between signal numbers, CE memory addresses, ...
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... Signal Number 1.2.5 Voltage References The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero tech- niques. The reference of the 71M6533H/71M6534H is trimmed in production to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coeffi- cient. The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU us- ing the I/O RAM register CHOP_E (0x2002[5:4]) ...
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FDS_6533_6534_004 voltage reference. The CHOP_E bits control the behavior of CROSS. The CROSS signal will reverse the amplifier connection in the voltage reference in order to negate the effects of its offset. On the first CK32 rising edge after the ...
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Data Sheet the CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery signals. IAP IAN VA IBP IBN VB ICP ICN VC ...
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FDS_6533_6534_004 Table 4 shows the CE addresses in XRAM allocated to analog inputs from the AFE. Table 4: XRAM Locations for ADC Results Address (HEX) 0x07 – 0x09 The CE is aided by support hardware to facilitate implementation of equations, ...
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Data Sheet 1.2.12 Pulse Generators The 71M6533 and 71M6534 provide four pulse generators, RPULSE, WPULSE, XPULSE and YPULSE, as well as hardware support for the RPULSE and WPULSE pulse generators. The pulse generators can be used to output CE ...
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FDS_6533_6534_004 1.2.14 CE Functional Overview The ADC processes one sample per channel per multiplexer cycle. samples taken during one multiplexer cycle (phases A, B, and C being processed). During an ALT mul- tiplexer sequence, missing samples are filled in by ...
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Data Sheet There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES (even though when SUM_CYCLES = 42, one set of SUM_CYCLES happens to sample a period of 16.6 ms). Furthermore, sampling does ...
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FDS_6533_6534_004 1.3 80515 MPU Core The 71M6533 and 71M6534 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 10 MHz clock results in a processing throughput of 10 MIPS. The 80515 architec- ture ...
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Data Sheet If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is dis- abled, the first 0x40 bytes of RAM are still unusable because the 71M6533/71M6534 ADC writes to these locations. ...
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FDS_6533_6534_004 The user switches between pointers by toggling the LSB of the DPS register. The values in the data poin- ters are not affected by the LSB of the DPS register. All DPTR related instructions use the currently se- lected ...
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Data Sheet Table 9: Special Function Register Map Bit Hex/ Addressable Bin X000 X001 F8 INTBITS IFLAGS WDCON D0 PSW C8 T2CON C0 IRCON B8 IEN1 IP1 IEN0 IP0 A0 ...
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FDS_6533_6534_004 Address Reset value Name (Hex) (Hex) S1BUF 0x9C 0x00 S1RELL 0x9D 0x00 IEN0 0xA8 0x00 IP0 0xA9 0x00 S0RELL 0xAA 0xD9 0xB8 0x00 IEN1 IP1 0xB9 0x00 S0RELH 0xBA 0x03 S1RELH 0xBB 0x03 PDATA 0xBF 0x00 IRCON 0xC0 0x00 ...
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Data Sheet Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08. Data Pointer: The data pointer ...
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FDS_6533_6534_004 Table 13: Stretch Memory Cycle Width Stretch CKCON[2:0] Value 000 001 010 011 100 101 110 111 1.3.4 71M6533/71M6534-Specific Special Function Registers Table 14 shows the location and description of the 71M6533/71M6534-specific SFRs. Table 14: 71M6533/71M6534 Specific SFRs Register ...
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Data Sheet Register SFR (Alternate Address Name) IFLAGS 0xE8[0] IE_XFER 0xE8[1] IE_RTC 0xE8[2] FW_COL0 0xE8[3] FW_COL1 0xE8[4] IE_PB 0xE8[5] IE_WAKE 0xE8[6] PLL_RISE 0xE8[7] PLL_FALL INT6 … INT0 INTBITS 0xF8[6:0] (INT0 … INT6) 0xF8[7] WD_RST Only byte operations on the ...
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FDS_6533_6534_004 transmission by the associated UART. Received data are available by reading from the receive buffer. Both UARTs can simultaneously transmit and receive data. WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers ...
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Data Sheet S1CON also recommended to have a timeout slightly longer than one character time on both inter- rupts that restarts the transmit or receive logic. Table 17: The S0CON (UART0) Register (SFR 0x98) Bit Symbol Function ...
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FDS_6533_6534_004 1.3.7 Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be confi- gured for counter or timer operations. In timer mode, the register is incremented every machine cycle, i.e. it ...
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Data Sheet Timer/Counter 0 If set, enables external gate control (signal INT0). When INT0 is high, TMOD[3] Gate and the TR0 bit is set (see the TCON register), a counter is incremented every falling edge on T0 input signal. ...
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FDS_6533_6534_004 Special Function Registers for Interrupts The following SFR registers control the interrupt functions: The interrupt enable registers: IEN0, IEN1 and IEN2 (see The Timer/Counter control registers, TCON and T2CON (see The interrupt request register, IRCON (see The interrupt priority ...
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Data Sheet Table 27: TCON Bit Functions (SFR 0x88) Bit Symbol Function TCON[7] TF1 Timer 1 overflow flag. TCON[6] TR1 Not used for interrupt control. TCON[5] TF0 Timer 0 overflow flag. Not used for interrupt control. TCON[4] TR0 TCON[3] ...
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FDS_6533_6534_004 The MPUs of the 71M6533 and 71M6534 allow seven external interrupts. These are connected as shown in Table 30. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in T2CON. ...
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Data Sheet IEN_SPI 20B0[4] 2007[4] EX_FWCOL EX_PLL 2007[5] The AUTOWAKE and PB flag bits are shown in even though they are not actually related to an interrupt. These bits are set by hardware when the MPU wakes from a ...
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FDS_6533_6534_004 Interrupt Sources and Vectors Table 36 shows the interrupts with their associated flags and vector addresses. Interrupt Re- quest Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 v1.1 © 2007-2009 TERIDIAN Semiconductor Corporation Table 35: ...
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Data Sheet ...
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FDS_6533_6534_004 1.4 On-Chip Resources 1.4.1 Oscillator The 71M6533/71M6534 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The oscillator has been designed specifically to handle these crystals and is ...
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Data Sheet The PLL has a 2x emulator clock which is controlled by ECK_DIS. Since clock noise from this feature may disturb the ADC recommended that this option be avoided when possible. The MPU clock frequency CKMPU ...
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... Physical Memory Flash Memory The device includes 128 KB (71M6533/H, 71M6534) or 256 KB (71M6534H) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM, MPU RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations ...
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... The program memory of the 71M6533/71M6534 consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The I/O RAM register FL_BANKis used to switch one of four (71M6533/H, 71M6534) or eight (71M6534H) memory banks each into the address range from 0x8000 to 0xFFFF. Note that when FL_BANK = 0, the upper bank is the same as the lower bank ...
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... FDS_6533_6534_004 Table 38: Bank Switching with FL_BANK[2:0] 71M6533/H 71M6534H 71M6534 FL_BANK[1:0] FL_BANK[2:0] 00 000 01 001 10 010 11 011 100 Not applicable 101 in 71M6533/H 110 and 71M6534 111 Program Security When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE op- erations are blocked. This guarantees the security of the user’ ...
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Data Sheet When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2, WPULSE, or VARPULSE. The configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately be configured as DIO_1. Its control is OPT_RXDIS. from ...
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FDS_6533_6534_004 Table 39: Data/Direction Registers and Internal Resources for DIO Pin Groups DIO PB 1 – – LCD Segment 71M6533 Pin # 97 91 71M6534 Pin # 114 109 Configuration (DIO Always DIO or LCD segment Data Register ...
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Data Sheet DIO 48 49 LCD Segment 68 69 71M6533 Pin # 23 24 71M6534 Pin # Configuration (DIO or LCD segment) LCD_BITMAP[71:64] LCD_BITMAP[80:72] Data Register Direction Register 0 = input output See ...
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FDS_6533_6534_004 Table 40: Selectable Resources using the DIO_Rn Bits DIO_Rn When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in Figure 9, right), not ...
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Data Sheet For each multi-use pin, the corresponding LCD_BITMAP[] register (as described in Section is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[] registers is speci- 4.1 I/O RAM Map –Functional fied ...
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FDS_6533_6534_004 Table 41: EECTRL Bits for 2-pin Interface Status Read/ Reset Name Bit Write State 7 ERROR R 6 BUSY R 5 RX_ACK R 4 TX_ACK R 3:0 W CMD[3:0] The EEPROM interface can also be operated by controlling the ...
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Data Sheet 3:0 CNT[3:0] W Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data will be read MSB first, and right justified into the low order bits of ...
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FDS_6533_6534_004 EECTRL Byte Written INT5 not issued Write -- No HiZ SCLK (output) SDATA (output) D7 SDATA output Z (LoZ) BUSY (bit) Figure 13: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written Write -- With HiZ and WFR SCLK ...
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Data Sheet SERIAL READ 8 bit CMD PCSZ 0 PSCK (From Host) PSDI (From 653X) PSDO SERIAL WRITE 8 bit CMD PCSZ 0 PSCK (From Host) PSDI (From 653X) PSDO Figure ...
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FDS_6533_6534_004 1.4.12 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6533/71M6534. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. ...
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Data Sheet TMUX[4:0] Mode 0 Analog 1 Analog 2 Analog 3 Analog 4 Analog 5 Analog 6 Analog 7 Analog – 0x0F 0x10 Digital 0x11 Digital – 0x12 0x13 Digital 0x14 Digital 0x15 Digital 0x16 Digital 0x17 ...
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FDS_6533_6534_004 2 Functional Description 2.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy [Wh ...
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Data Sheet 2.2 System Timing Summary Figure 18 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and the two serial output streams. In this example, MUX_DIV=6 and FIR_LEN=2 (384). The duration of each MUX frame ...
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FDS_6533_6534_004 2.3 Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the ...
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Data Sheet 2.3.1 BROWNOUT Mode In BROWNOUT mode, most non-metering digital functions are active (as shown in Table 45) including ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a low-bias current regulator will provide 2.5 Volts to V2P5 ...
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FDS_6533_6534_004 2.3.2 LCD Mode In LCD mode, the data contained in the LCD_SEG registers is displayed four LCD segments con- nected to the pin SEG18 can be made to blink without the involvement of the MPU, which is ...
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Data Sheet VREF IAP IAN VA IBP VBIAS MUXP IBN VB VADC ICP ICN VC VREF VREF_CAL EQU VREF_DIS MUX_AL MUX_DIV VBAT TEMP 2.5V_NV RTCLK (32KHz) OSC XIN MPU_DIV (32KHz) CKOUT_E XOUT RTCA_ADJ ...
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FDS_6533_6534_004 VREF IAP IAN VA IBP VBIAS MUXP IBN VB VADC ICP ICN VREF VREF_CAL EQU VREF_DIS MUX_AL MUX_DIV VBAT TEMP 2.5V_NV RTCLK (32KHz) OSC XIN MPU_DIV (32KHz) CKOUT_E XOUT RTCA_ADJ RTC 2.5V_NV ...
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Data Sheet VREF IAP IAN VA IBP VBIAS MUXP IBN VB VADC ICP ICN VREF VREF_CAL EQU VREF_DIS MUX_AL MUX_DIV VBAT TEMP 2.5V_NV RTCLK (32KHz) OSC XIN MPU_DIV (32KHz) CKOUT_E XOUT RTCA_ADJ ...
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FDS_6533_6534_004 System (V3P3SYS) V1_OK Battery Current BROWNOUT MPU Mode WAKE MPU Clock Source PLL_OK Figure 24: Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal ...
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Data Sheet VBAT Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ VBAT_OK Figure 26: Power-Up Timing with VBAT only 2.4 Fault and Reset Behavior 2.4.1 Reset Mode When the RESET pin is pulled high, all digital ...
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FDS_6533_6534_004 If there is no battery when system power returns, the part will switch to MISSION mode when PLL_OK rises. All configuration bits will be in reset state, and RTC and MPU RAM data will be unknown and must be ...
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Data Sheet readies the timer to start when the processor writes to the SLEEP or LCD_ONLY registers. The timer is reset and disarmed whenever the processor is awake. Thus desired to wake the MPU periodically (every ...
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... RAM registers TRIMBGA, TRIMBGB, TRIMM[2:0]. The MPU can read these trim fuses and calculate the correction coefficients PPM1 and PPMC2 per the formulae given in Section 3.5 Temperature Compensation for additional details. The fuse TRIMBGB is non-zero for the 71M6533H/71M6534H part and zero for the 71M6533/71M6533 part. v1.1 © 2007-2009 TERIDIAN Semiconductor Corporation VA = Vin * R ...
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... TRIMT[7:0] I/O RAM register. TC1 and TC2 allow compensation for variations of the reference vol- tage to within ±40 PPM/°C. For the 71M6533H/71M6534H, individualized coefficients TC1 and TC2 can be retrieved from the on-chip fuses via TRIMBGA, TRIMBGB, TRIMM[2:0] (see Section 71M6533H/71M6534H Parts). ...
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FDS_6533_6534_004 Since TC1 and TC2 are given in µV/°C and µV/°C (1.195V) has to be taken into account when transitioning to PPM/°C and PPM/°C that PPMC = 26.84*TC1/1.195 and PPMC2 = 1374*TC2/1.195). 3.5.2 Temperature Compensation for VREF The bandgap temperature ...
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Data Sheet The following dedicated and multi-use pins can be assigned as LCD segments: 15 dedicated LCD segment pins: SEG0 to SEG2, SEG8, SEG12 to SEG18, SEG20 to SEG23. 9 dual-function pins: MUX_SYNC/SEG7, CKTEST/SEG19, E_RXTX/SEG9, E_TCLK/SEG10, E_RST/SEG11, SEG3/PCLK, SEG4/PSDO, ...
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FDS_6533_6534_004 3.8 Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 35 and described below: DIO5 connects to both the DI and DO pins of the ...
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Data Sheet 3.10 Optical Interface (UART1) The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232 tran- sceiver for example), or they can be used to directly operate optical components (for example, ...
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FDS_6533_6534_004 V3P3 GND 3.12 Connecting the Reset Pin Even though a functional meter will not necessarily need a reset switch useful to have a reset push- button for prototyping as shown in V3P3SYS (functional in MISSION mode only), ...
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Data Sheet V3P3D 62 Ω 62 Ω 62 Ω Figure 40: External Components for the Emulator Interface 3.14 Connecting a Battery It is important that a valid voltage is connected to the VBAT pin at all times. For meters ...
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FDS_6533_6534_004 3.16 MPU Firmware Library All application-specific MPU functions mentioned in Teridian as a standard ANSI C library and as ANSI C source code. The code is available as part of the Demonstration Kit for the 71M6533/71M6534. The Demonstration Kits ...
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Data Sheet 4 Firmware Interface 4.1 I/O RAM Map –Functional Order Bits marked with an asterisk (e.g. UMUX_E*) apply to the 71M6534 only. Name Address Bit 7 Configuration: CE0 2000 EQU[2:0] CE1 2001 PRE_SAMPS[1:0] CE2 2002 Not Used COMP0 ...
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FDS_6533_6534_004 Name Address Bit 7 DIO6 200E Not Used 200F Reserved (00) UMUX_E* UMUX_SEL* DIO7/ P0 SFR 80 DIO8 SFR A2 SFR 90 DIO9 / P1 DIO_1[7:5] (Port 1) DIO10 SFR 91 DIO_DIR1[7:5] DIO11/ P2 SFR A0 DIO_2[7] Not Used ...
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Data Sheet Name Address Bit 7 RTC5 201A Not Used Not Used RTC6 201B RTCADJ_H 201C Not Used Not Used RTCADJ_M 201D RTCADJ_L 201E WE 201F LCD Display Interface: LCDX 2020 MUX_SYNC_E LCDY 2021 Not Used LCD_Y LCD_MAP0 2023 ...
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FDS_6533_6534_004 Name Address Bit 7 Pulse Generator: PLS_W 2080 PLS_I 2081 ADC Mux: SLOT0 2090 2091 SLOT1 SLOT2 2092 SLOT3 2093 SLOT4 2094 SLOT5 2096 SLOT6 2097 SLOT7 2098 SLOT8 2099 209A SLOT9 SPI Interrupt: SPI0 20B0 Not Used Not ...
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Data Sheet 4.2 I/O RAM Description – Alphabetical Order The following conventions apply to the descriptions in this table: Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in ...
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FDS_6533_6534_004 0 CKOUT_E 2004[4] -- 2003[0] COMPSTAT 2009[2:0] 0 DI_RPB[2:0] 2009[6:4] 0 DIO_R1[2:0] DIO_R2[2:0] 200A[2:0] 0 200A[6:4] 0 DIO_R3[6:4] 200B[2:0] 0 DIO_R4[2:0] 200B[6:4] 0 DIO_R5[2:0] 200C[2:0] 0 DIO_R6[2:0] DIO_R7[2:0] 200C[6:4] 0 200D[2:0] 0 DIO_R8[2:0] 200D[6:4] 0 DIO_R9[2:0] 200E[2:0] 0 DIO_R10[2:0] ...
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Data Sheet DIO_0[7:0] SFR 80 0 DIO_1[7:0] SFR 90 0 DIO_2[7:0] SFR A0 0 DIO_3[6:0] SFR B0 0 DIO_EEX[1:0] 2008[7:6] 0 DIO_PV 2008[2] 0 DIO_PW 2008[3] 0 DIO_PX 200F[3] 0 200F[2] 0 DIO_PY SFR 9E 0 EEDATA[7:0] EECTRL[7:0] SFR ...
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FDS_6533_6534_004 FIR_LEN[1:0] 2007[3:2] 1 FL_BANK[1:0] SFR B6[1:0] 1 FL_BANK[2:0]* SFR B6[2:0] FLSH_ERASE SFR 94[7:0] 0 [7:0] FLSH_MEEN SFR B2[1] 0 FLSH_PGADR SFR B7 [7:2] 0 [5:0] FLSH_PWE SFR B2[0] 0 FOVRIDE 20FD[4] 0 v1.1 1 R/W FIR_LEN[1:0] controls the length ...
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Data Sheet GP0 20C0 0 … … … GP7 20C7 0 IE_FWCOL0 SFR E8[2] 0 IE_FWCOL1 SFR E8[3] 0 SFR E8[4] 0 IE_PB IE_PLLRISE SFR E8[6] 0 IE_PLLFALL SFR E8[7] 0 20B0[4] IEN_SPI IEN_WD_NROVF 20B0[0] 0 IE_XFER SFR E8[0] ...
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FDS_6533_6534_004 LCD_BITMAP 2026[2:0] 0 [50:48] LCD_BITMAP 2027[7:5,3:0] 0 [63:61], [59:56]* LCD_BITMAP 2028[7:0] 0 [71:64] LCD_BLKMAP18 205A[3:0] 0 [3:0] LCD_CLK[1:0] 2021[1:0] 0 20AB[3:1] 0 LCD_DAC[2:0] LCD_E 2021[5] 0 v1.1 L R/W Configuration for DIO30/SEG50 through DIO28/SEG48. LCD_BITMAP[48] correspond- ing to DIO28/SEG48 ...
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Data Sheet LCD_MODE[2:0] 2021[4:2] 0 LCD_ONLY 20A9[5] 0 LCD_SEG0[3:0] 2030[3:0] 0 … … … LCD_SEG18[3:0] 2042[3:0] 0 LCD_SEG19[3:0] 2043[3:0] 0 … … … LCD_SEG31[3:0] 204F[3:0] 0 LCD_SEG32[3:0]* 2050[3:0] 0 LCD_SEG33[3:0] 2051[3:0] 0 … … … LCD_SEG41[3:0] 2059[3:0] 0 LCD_SEG42[3:0]* ...
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FDS_6533_6534_004 LCD_SEG63[3:0] 2045[7:4] 0 … … … LCD_SEG65[3:0] 2047[7:4] 0 LCD_SEG66[3:0]* 2048[7:4] 0 LCD_SEG67[3:0] 2049[7:4] 0 … … … 204D[7:4] 0 LCD_SEG71[3:0] LCD_SEG72[3:0]* 204E[7:4] 0 … … … LCD_SEG75[3:0]* 2051[7:4] 0 LCD_Y 2021[6] 0 2005[4] 0 M26MHZ M40MHZ 2005[0] 0 ...
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Data Sheet MUX_DIV[3:0] 209D[3:0] 0 MUX_SYNC_E 2020[7] 0 OPT_FDC[1:0] 2007[1:0] 0 OPT_RXDIS 2008[5] 0 OPT_RXINV 2008[4] 0 OPT_TXE[1:0] 2007[7:6] 00 OPT_TXINV 2008[0] 0 OPT_TXMOD 2008[1] 0 PLL_OK 2003[6] 0 PLS_MAXWIDTH 2080[7:0] FF [7:0] PLS_INTERVAL 2081[7:0] 0 [7:0] 2004[6] 0 ...
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FDS_6533_6534_004 PREG[16:0] 201C[2:0] 4 201D[7:0] 0 201E[7:2] 0 PRE_SAMPS[1:0] 2001[7:6] 0 QREG[1:0] 201E[1:0] 0 RST_SUBSEC 2010[0] 0 RTCA_ADJ[6:0] 2011[6:0] 40 2015 * RTC_SEC[5:0 2016 * RTC_MIN[5:0] 2017 * RTC_HR[4:0] 2018 * RTC_DAY[2:0] 2019 * RTC_DATE[4:0] 201A * RTC_MO[3:0] 201B * ...
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Data Sheet SLEEP 20A9[6] 0 SEL_IAN 20AC[1] 0 SEL_IBN 20AC[5] 0 20AD[1] 0 SEL_ICN SEL_IDN 20AD[5] 0 SLOT0_SEL[3:0] 2090[3:0] 0 2090[7:4] 1 SLOT1_SEL[3:0] … … SLOT8_SEL[3:0] 8 2094[3:0] 9 SLOT9_SEL[3:0] 2094[7:4] SLOT0_ALTSEL 10 2096[3:0] [3:0] 1 SLOT1_ALTSEL 2096[7:4] [3:0] ...
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... TRIMBGA 6 TRIMBGB Contains TRIMBGA,TRIMBGB or TRIMM[2:0] depending on the value written to 0 R/W TRIMSEL[3:0]. If TRIMBGB = 0, the device is a 71M6533/71M6534, else 71M6533H/71M6534H. 0 R/W Enables the optical UART multiplexer, selects the alternate function (MTX, MRX) for DIO8, DIO9. 0 R/W When UMUX_E = 1, selects between OPT_TX, OPT_RX and MTX, MRX as the optical UART I/O pins ...
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Data Sheet WD_OVF 2002[ 201F[7:0] WRPROT_BT SFR B2[5] 0 WRPROT_CE SFR B2[ The WD overflow status bit. This bit is set when the WD timer overflows powered 0 R/W by the nonvolatile supply ...
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FDS_6533_6534_004 4.3 CE Interface Description 4.3.1 CE Program The CE performs the precision computations necessary to accurately measure power. These computa- tions include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase ...
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Data Sheet 4.3.4 Environment Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by implementing the following steps: Load the CE data into RAM. Establish the equation to be ...
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FDS_6533_6534_004 Name CE TEMP FIR data 0x0A VBAT FIR data 0x0B … Chip ID, Version bytes 0x0F … Last Address 0x3FF 4.3.7 CE Status and Control The CE Status Word is useful for generating early warnings to the MPU (Table ...
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Data Sheet The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE) temperature compensation is enabled. I0_SHUNT, I1_SHUNT and I2_SHUNT can configure their respective current inputs to accept shunt resistor sensors. In ...
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FDS_6533_6534_004 PULSE_SLOW [0] Table 54: Sag Threshold and Gain Adjust Control CE Ad- Name Default dress 0x24 SAG_THR 2.39*10 0x40 GAIN_ADJ 16384 4.3.8 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available ...
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Data Sheet Instantaneous Energy Measurement Variables IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumu- lation interval. INSQSUM_X can be used for computing the neutral current. Table 56: CE Energy Measurement Variables CE ...
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FDS_6533_6534_004 CE Ad- Name dress 0x98 PH_AtoC_X 0x83 MAINEDGE_X 4.3.9 Other Measurement and Control Parameters Temperature Measurement and Temperature Compensation Table 58 describes the CE registers supporting temperature measurement and temperature compensation. CE Ad- Name dress 0x81 TEMP_RAW 0x9D TEMP_X ...
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Data Sheet The maximum time jitter is1/6 of the MUX cycle period (nominally 67 µs) and is independent of the num- ber of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is ...
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FDS_6533_6534_004 0x2E QUANT_IA 0 0x2F 0 QUANT_IB 0x30 QUANT_IC 0 0x35 0x63653333 0x36 0x61303463 0x37 0x00000000 4.3.10 CE Calibration Parameters Table 61 lists the parameters that are typically entered to effect calibration of meter accuracy. CE Ad- Name Default dress ...
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Data Sheet multiplexer 2520Hz Figure 42: CE Data Flow: Multiplexer and ADC IA_RAW OFFSET x NULL F0 CAL_IA VA_RAW OFFSET x NULL F0 CAL_VA ...other phases F0 Generator Figure 43: ...
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FDS_6533_6534_004 VARA VARB VARC PRE_SAMPS SQUARE Figure 44: CE Data Flow: Squaring and Summation Stages v1.1 © 2007-2009 TERIDIAN Semiconductor Corporation SUM WASUM_X WBSUM_X Σ WCSUM_X ...
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Data Sheet 5 Specifications 5.1 Absolute Maximum Ratings Table 62 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Rat- ings may cause permanent damage to the device. These are stress ratings only and functional operation ...
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FDS_6533_6534_004 5.2 Recommended External Components Table 63: Recommended External Components Name From To C1 V3P3A AGND C2 V3P3D DGND CSYS V3P3SYS DGND C2P5 V2P5 DGND XTAL XIN XOUT CXS XIN AGND CXL XOUT AGND Notes: 1. AGND and DGND should ...
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Data Sheet 5.4 Performance Specifications 5.4.1 Input Logic Levels Parameter a Digital high-level input voltage , V a Digital low-level input voltage , V Input pull-up current E_RXTX, E_ISYNC E_RST, CKTEST Other digital inputs Input pull down ...
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... Condition FIR_LEN=0 (L=138) FIR_LEN=1 (L=288) (L=384) FIR_LEN=2 FIR_LEN=0 (L=186) (L=384) FIR_LEN=1 (L=588) FIR_LEN=2 Condition BROWNOUT mode 71M6533/6533H 71M6534H LCD Mode LCD DAC off LCD DAC on SLEEP Mode Condition | ≤ V3P3D | ≤ V3P3D 71M6533/71M6534 Data Sheet Min Typ Max Unit kΩ ...
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Data Sheet 5.4.8 2.5 V Voltage Regulator Unless otherwise specified, the load = 5 mA. Table 72: 2.5 V Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Voltage overhead V3P3SYS-V2P5 PSSR V2P5/ V3P3 5.4.9 Low-Power Voltage Regulator Unless ...
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FDS_6533_6534_004 5.4.13 LCD Drivers The information in Table 77 applies to all COM and SEG pins with LCD_DAC[2:0] = 000. Table 77: LCD Driver Performance Specifications Parameter VLC2 Voltage † VLC1 Voltage , ⅓ bias ½ bias ½ bias, minimum ...
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... Table 79: VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF chop step VREF power supply sensitivity ΔVREF / ΔV3P3A VREF input impedance VREF output impedance a VNOM definition If TRIMBGA and TRIMBGB are available (71M6533H/71M6534H) Definitions VNOM temperature coefficients TC1 TC2 VREF(T) deviation from VNOM(T) 6 VREF ( T ...
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FDS_6533_6534_004 5.4.16 ADC Converter, V3P3A Referenced Table 80 shows the performance specifications for the ADC converter, V3P3A referenced. For this data, FIR_LEN=2, [M40MHZ, M26MHZ]=[00], unless stated otherwise, VREF_DIS=0. LSB values do not include the 8-bit left shift at the CE ...
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Data Sheet 5.5 Timing Specifications 5.5.1 Flash Memory Table 81: Flash Memory Timing Specifications Parameter Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations Write Time ...
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FDS_6533_6534_004 5.5.5 SPI Slave Port (MISSION Mode) Table 85: SPI Slave Port (MISSION Mode) Timing Parameter t PCLK cycle time SPIcyc t Enable lead time SPILead t Enable lag time SPILag t PCLK pulse width: SPIW High Low t PCSZ ...
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Data Sheet 5.6 Typical Performance Data 5.6.1 Accuracy over Current Figure 46 shows meter accuracy over current for various line frequencies. Figure 47 shows meter accu- racy over current at various load angles. 6533/34 Wh Performance, Equation 5, 45 ...
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... Accuracy over Temperature With digital temperature compensation enabled, the temperature characteristics of the reference voltage (VREF) are compensated to within ±40 PPM/°C for the 71M6533/71M6534 and within ±15 PPM/°C for the 71M6533H/71M6534H. 5.7 Package Outline Drawings 5.7.1 71M6533 (100 Pin LQFP) Controlling dimensions are in mm. ...
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Data Sheet 5.7.2 71M6534/6534H (120 Pin LQFP) Controlling dimensions are in mm. 7.000 120 1 13.950 +/- 0.100 0.180 +/- 0.050 Figure 49: 71M6534/6534H 120-pin LQFP Package Outline 114 © 2007-2009 TERIDIAN Semiconductor Corporation 16.000 +/- 0.200 14.000 +/- ...
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FDS_6533_6534_004 5.8 Pinout 5.8.1 71M6533/71M6533H Pinout (100 Pin LQFP) GNDD 1 SEG9/E_RXTX 2 DIO2/OPT_TX 3 TMUXOUT SEG3/PCLK 6 V3P3D 7 SEG19/CKTEST 8 V3P3SYS 9 SEG4/PSDO 10 SEG5/PCSZ 11 SEG37/DIO17 12 SEG38/DIO18/MTX 13 DIO56 14 DIO57 15 DIO58 ...
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... SEG37/DIO17 17 SEG38/DIO18/MTX 18 DIO56 19 DIO57 20 DIO58 21 DIO3 22 COM0 23 COM1 24 COM2 25 COM3 26 SEG67/DIO47 27 SEG68/DIO48 28 SEG69/DIO49 29 SEG70/DIO50 30 Figure 51: Pinout for 71M6534/71M6534H LQFP-120 Package 116 © 2007-2009 TERIDIAN Semiconductor Corporation Teridian 71M6534/ 71M6534H FDS_6533_6534_004 SEG59/DIO39 90 SEG58/DIO38 89 SEG57/DIO37 88 SEG56/DIO36 87 GNDD 86 RESET 85 V2P5 84 VBAT SEG48/DIO28 81 SEG31/DIO11 ...
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FDS_6533_6534_004 5.9 Pin Descriptions Pins marked with an asterisk (e.g. V2*) are only available on the 71M6534. 5.9.1 Power and Ground Pins Name Type Circuit Description – GNDA P Analog ground: This pin should be connected directly to the ground ...
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Data Sheet 5.9.3 Digital Pins Name Type Circuit Description COM3,COM2 COM1,COM0 SEG0…SEG2 SEG8, SEG12…SEG18, SEG20…SEG23 SEG24/DIO4 I … SEG31/DIO11, SEG32/DIO12* SEG33/DIO13 … SEG41/DIO21, SEG42/DIO22* SEG43/DIO23 … SEG47/DIO27, SEG48/DIO28* SEG49/DIO29, SEG50/DIO30, SEG56/DIO36* … ...
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FDS_6533_6534_004 Type Name Cicuit E_RXTX/SEG9 I E_RST/SEG11 I E_TCLK/SEG10 ICE_E I 2 CKTEST/SEG19 MUXSYNC/SEG7 TMUXOUT O 4 OPT_RX/DIO1 I OPT_TX/DIO2 I RESET I 2 ...
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Data Sheet 5.9.4 I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin ...
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... LQFP Lead Free, 0.1% 256 KB bulk 120-pin LQFP Lead Free, 0.5% 128 KB tape and reel 71M6534-IGTR/F 71M6534 71M6534H 120-pin LQFP Lead Free, 0.1% 256 KB tape and reel 71M6534H-IGTR/F 71M6534H-IGT 7 Related Information The following documents related to the 71M6533 and 71M6534 are available from Teridian Semiconduc- ...
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Data Sheet Appendix A: Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response ICE In-Circuit Emulator IEC International Electrotechnical ...
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FDS_6533_6534_004 Appendix B: Revision History Revision Date 1.0 March 6, 2009 1.1 November 9, 2009 v1.1 © 2007-2009 TERIDIAN Semiconductor Corporation Description First publication with changes with respect to the preliminary data sheet (PDS) as follows: 1) Corrected reversed labels ...
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Data Sheet © 2008 Teridian Semiconductor Corporation. All rights Reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. TM Simplifying System Integration Intel is a registered trademark of Intel Corporation. All other trademarks are the property ...