71m6521fe Maxim Integrated Products, Inc., 71m6521fe Datasheet
71m6521fe
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71m6521fe Summary of contents
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... VOLTAGE REF VREF VBIAS SERIAL PORTS TX AMR RX RX/DIO1 SENSE IR TX/DIO2 DRIVE/MOD COMPARATOR POWER V1 FAULT OSC/PLL XIN 32 kHz XOUT v1.0 71M6521DE/71M6521FE 2 C, μWire POWER SUPPLY V3.3 V3.3A GNDA GNDD SYS PWR MODE CONTROL WAKE-UP REGULATOR VBAT V2.5 BATTERY TEMP DIO, PULSE SENSOR RAM 3.3V LCD COM0..3 88 ...
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... Interrupts .........................................................................................................................................29 On-Chip Resources .......................................................................................................................................37 Oscillator..........................................................................................................................................37 PLL and Internal Clocks...................................................................................................................37 Real-Time Clock (RTC) ...................................................................................................................37 Temperature Sensor........................................................................................................................37 Physical Memory .............................................................................................................................38 Optical Interface ..............................................................................................................................39 Digital I/O.........................................................................................................................................39 LCD Drivers .....................................................................................................................................41 Battery Monitor ................................................................................................................................42 EEPROM Interface ..........................................................................................................................42 Hardware Watchdog Timer..............................................................................................................45 Page 101 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 v1.0 ...
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... I/O RAM MAP – In Numerical Order ..............................................................................................................70 SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order ..........................................................71 I/O RAM DESCRIPTION – Alphabetical Order ..............................................................................................72 CE Interface Description ................................................................................................................................79 CE Program.....................................................................................................................................79 Formats ...........................................................................................................................................79 Constants ........................................................................................................................................79 Environment ....................................................................................................................................79 v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 Page 101 ...
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... PINOUT (LQFP-64) .......................................................................................................................................96 PINOUT (QFN 68) .........................................................................................................................................96 Recommended PCB Land Pattern for the QFN-68 Package .........................................................................97 PIN DESCRIPTIONS .....................................................................................................................................98 Power/Ground Pins:.........................................................................................................................98 Analog Pins: ....................................................................................................................................98 Digital Pins:......................................................................................................................................99 I/O Equivalent Circuits: .................................................................................................................. 100 ORDERING INFORMATION ....................................................................................................................... 101 Page 101 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 v1.0 ...
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... Figure 39: External Components for the Emulator Interface ........................................................................................69 Figure 40: Wh Accuracy, 0.1A to 200A at 240V/50Hz and Room Temperature...........................................................93 Figure 41: Meter Accuracy over Harmonics at 240V, 30A............................................................................................93 Figure 42: Typical Meter Accuracy over Temperature Relative to 25°C.......................................................................94 v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ...
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... Table 41: The TCON Register......................................................................................................................................31 Table 42: The TCON Bit Functions ..............................................................................................................................31 Table 43: The T2CON Bit Functions ............................................................................................................................31 Table 44: The IRCON Register ....................................................................................................................................32 Table 45: The IRCON Bit Functions.............................................................................................................................32 Table 45: External MPU Interrupts ...............................................................................................................................32 Page 101 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 v1.0 ...
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... Table 60: Available Circuit Functions (“—“ means “not active).....................................................................................50 Table 61: Frequency over Temperature .......................................................................................................................61 Table 62: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package .......................................................64 Table 63: LCD and DIO Pin Assignment by LCD_NUM for the LQFP-64 Package......................................................65 v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ...
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... OPT_RX/ OPTICAL DIO1 OPT_TX/ MOD DIO2/ OPT_RXDIS WPULSE/ OPT_RXINV OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT V1 COMP_STAT Page 101 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 PLL ADC 32KHz CKADC 4 ...
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... PLL and voltage allpass networks not replaced in the ALT mux selections. Table 1 details the regular and alternative MUX sequences. Missing samples due to an ALT multiplexer sequence are filled in by the CE. v1.0 71M6521DE/71M6521FE Hardware Overview Analog Front End (AFE) © ...
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... CHOP_E (0x2002[5:4]). The two bits in the CHOP_E register enable the MPU to operate the chopper circuit in regular or inverted operation “toggling” mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the measured signals will automatically be averaged out. The general topology of a chopped amplifier is given in Figure 2. Page 101 71M6521DE/71M6521FE Mux State ...
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... The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section titled “Temperature Compensation”). v1.0 71M6521DE/71M6521FE ...
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... Each CE instruction word is two bytes long. Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends Page 101 71M6521DE/71M6521FE VREF VBIAS ...
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... The register EQU (located in the I/O RAM) specifies the equation to be used based on the number of phases used for metering. EQU 1 element, 2W 1φ with neutral current sense 0 and tamper detection (VA connected to VB element, 3W 1φ element, 4W 2φ v1.0 71M6521DE/71M6521FE NAME DESCRIPTION 00 IA Phase A current 01 VA Phase A voltage 02 IB ...
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... For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available. Page 101 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET ...
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... It is important to note that the length of the accumulation interval, as determined by N PRE_SAMPS, is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting accumulation interval is: τ This means that accurate time measurements should be based on the RTC, not the accumulation interval. v1.0 71M6521DE/71M6521FE 13/32768Hz = 397µs ...
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... Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low order bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very slow external RAM or external peripherals. Page 101 71M6521DE/71M6521FE 80515 MPU Core Memory Type Typical Usage ...
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... The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM. v1.0 71M6521DE/71M6521FE Stretch Value Read signals width memaddr ...
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... Only a few addresses are occupied, the others are not implemented. SFRs specific to the 652X are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. The registers at 0x80, 0x88, 0x90, etc., are bit-addressable, all others are byte-addressable. Page 101 71M6521DE/71M6521FE Direct addressing Indirect addressing Byte-addressable area Bit-addressable area Register banks R0… ...
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... WDCON 0xE0 0x00 A 0xF0 0x00 B Table 8: Special Function Registers Reset Values v1.0 71M6521DE/71M6521FE Description Port 0 Stack Pointer Data Pointer Low 0 Data Pointer High 0 Data Pointer Low 1 Data Pointer High 1 Watchdog Timer Reload register UART Speed Control Timer/Counter Control Timer Mode Control ...
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... MOV DPL,#data8 generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively). Program Counter: The program counter (PC bytes wide initialized to 0x0000 after reset. This register is incremented when fetching operation code or when operating on data from program memory. Page 101 71M6521DE/71M6521FE F0 RS1 RS OV Table 9: PSW Register Flags F0 is not to be confused with the F0 flag in the CE STATUS register ...
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... PGADDR FLSH_PGADR 0x9E EEDATA 0x9F EECTRL v1.0 71M6521DE/71M6521FE Table 11: Port Registers R/W Description W This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle (default = 0x00). ...
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... The 71M6521DE/FE includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second UART (UART1) is connected to the optical port, as described in the optical port description. Page 101 71M6521DE/71M6521FE R/W Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer to XRAM Space, normal operation (default). 1 – ...
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... The function of the UART0 depends on the setting of the Serial Port Control Register S0CON. MSB SM0 SM1 Serial Interface 1 Control Register (S1CON). The function of the serial port depends on the setting of the Serial Port Control Register S1CON. v1.0 71M6521DE/71M6521FE Using Internal Baud Rate Generator smod / (384 * (256-TH1 N/A ...
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... Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be S1CON.1 TI1 cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must S1CON.0 RI1 be cleared by software Page 101 71M6521DE/71M6521FE SM21 REN1 TB81 RB81 Table 16: The S1CON register Mode Description SM0 ...
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... IE0 int0 is observed. Cleared when an interrupt is processed. Interrupt 0 type control bit. Selects either the falling edge or low level on input TCON.0 IT0 pin to cause interrupt. v1.0 71M6521DE/71M6521FE TF0 TR0 IE1 IT1 Table 19: The TCON Register Table 20: The TCON Register Bit Functions © 2005-2008 TERIDIAN Semiconductor Corporation ...
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... Timer 0 acts as two independent 8-bit Timer/Counters. Note: In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow. Page 101 71M6521DE/71M6521FE M1 M0 GATE C/T ...
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... WDTREL register and the WDT is automatically reset. Since the WDT requires exact timing, firmware needs to be designed with special care in order to avoid unwanted WDT resets. TERIDIAN strongly discourages the use of the software WDT. v1.0 71M6521DE/71M6521FE Timer 1 Mode 0 Mode 1 YES ...
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... Note: The remaining bits in the IEN1 register are not used for watchdog control Interrupt Priority 0 Register (IP0): MSB -- WDTS Page 101 71M6521DE/71M6521FE ET2 ES0 ET1 EX1 Table 27: The IEN0 Register (see also Table 32) Table 28: The IEN0 Bit Functions (see also Table 32) ...
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... Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. v1.0 71M6521DE/71M6521FE Table 32: The IP0 bit Functions (see also Table 45) 5 ...
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... MSB SWDT Bit IEN1.7 IEN1.6 IEN1.5 IEN1.4 IEN1.3 IEN1.2 IEN1.1 IEN1.0 Page 101 71M6521DE/71M6521FE ES0 ET1 Table 35: The IEN0 Register Symbol Function EAL=0 – disable all interrupts EAL Not used for interrupt control WDT - ES0=0 – disable serial channel 0 interrupt ES0 ET1=0 – ...
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... Polarity control for INT3 falling edge, 1 – rising edge T2CON.6 I3FR Polarity control for INT3 falling edge, 1 – rising edge T2CON.5 I2FR Not used TCON.4 … -- T2CON0 v1.0 71M6521DE/71M6521FE - - - Table 39: The IEN2 Register Table 40: The IEN2 Bit Functions TF0 TR0 IE1 Table 41: The TCON Register Table 42: The TCON Bit Functions Table 43: The T2CON Bit Functions © ...
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... IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags, IE_XFER through IE_PB, are cleared by writing a zero to them. Since these bits are in a bit-addressable SFR byte, common practice Page 101 71M6521DE/71M6521FE EX6 IEX5 IEX4 ...
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... MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 47), and these interrupts must be cleared by the MPU software. v1.0 71M6521DE/71M6521FE Interrupt Flag NAME LOCATION ...
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... OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 47) and these interrupts must be cleared by the MPU software. Interrupt Priority 0 Register (IP0) MSB -- WDTS Note: WDTS is not used for interrupt controls Interrupt Priority 1 Register (IP1) MSB - - Page 101 71M6521DE/71M6521FE Serial channel 1 interrupt - - - - - - Table 48: Priority Level Groups IP0.5 IP0.4 IP0.3 Table 49: The IP0 Register IP1 ...
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... Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 v1.0 71M6521DE/71M6521FE External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Table 52: Interrupt Polling Sequence ...
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... IE_PLLFALL UART0 EEPROM I2C XF ER_BUSY IE_XFER RTC_1S IE_RTC Page 101 71M6521DE/71M6521FE L ogi rru pt Polarity Control Select ion Reg IEN0.7 > IRCON IRCON.2 IRCON.3 > ...
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... MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section titled “Temperature Compensation”). v1.0 71M6521DE/71M6521FE On-Chip Resources - MPU_DIV Hz where MPU_DIV varies from (MPU_DIV power- © ...
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... Physical Memory Flash Memory: The 71M6521DE/FE includes 16KB (71M6521DE) or 32KB (71M6521FE) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. ...
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... Table 55 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register. Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in the Applications section and in the I/O RAM Description under LCD_NUM[4:0]. v1.0 71M6521DE/71M6521FE VARPULSE WPULSE DIO2 MOD ...
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... This limitation applies to any pin that can be configured as a LCD driver. The control resources selectable for the DIO pins are listed in Table 56. If more than one input is connected to the same resource, the resources are combined using a logical OR. Page 101 71M6521DE/71M6521FE ...
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... The LCD interface is flexible and can drive either digit segments or enunciator symbols. Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5Hz or 1Hz. The blink rate is controlled by LCD_Y. There can four pixels/segments connected to each of these drivers. LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. v1.0 71M6521DE/71M6521FE 71M6521 71M6521 3.3V 3.3V ...
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... RX_ACK TX_ACK CMD[3:0 3 Page 101 71M6521DE/71M6521FE Polarity Description Positive 1 when an illegal command is received. Positive 1 when serial data bus is busy. Negative 0 indicates that the EEPROM sent an ACK bit. Negative 0 indicates when an ACK bit has been sent to the EEPROM CMD ...
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... SDATA output Z BUSY (bit) Figure 9: 3-Wire Interface. Write Command, HiZ=0. v1.0 71M6521DE/71M6521FE Description Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence ...
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... Figure 12: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written Write -- With HiZ and WFR SCLK (output) SDATA (out/in) D7 SDATA output Z BUSY (bit) Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1. Page 101 71M6521DE/71M6521FE CNT Cycles (6 shown (LoZ) CNT Cycles (8 shown ...
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... Inadvertently setting this bit will inhibit access to the part via the ICE SECURE interface mechanism for actively resetting the part between reset and erase operations is provided (see ICE Interface description). v1.0 71M6521DE/71M6521FE © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ...
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... Digital 0x19 Digital 0x1A Digital 0x1B Digital 0x1C 0X1D Digital 0X1E Digital 0X1F Digital Page 101 71M6521DE/71M6521FE Function DGND Reserved DGND Reserved VBIAS Not used -- Reserved -- Not used RTM (Real time output from CE) WDTR_EN (Comparator 1 Output AND V1LT3) Not used ...
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... The application of 240VAC and 100A results in an accumulation of 480Ws (= 0.133Wh) over the 20ms period, as indicated by the Accumulated Power curve. The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. v1.0 71M6521DE/71M6521FE Theory of Operation t ∫ ...
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... THE PRECISE FREQUENCY 150*CRYSTAL FREQUENCY = 4.9152MHz. 3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES. Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers. Page 101 71M6521DE/71M6521FE System Timing Summary ADC MUX Frame Conversions, MUX_DIV=1 (4 conversions) is shown MUX_DIV ...
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... The battery voltage must stay above 3V to ensure that BAT_OK remains true. Under this condition, the 71M6521DE/FE stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK true). Table 60 shows the circuit functions available in each operating mode. v1.0 71M6521DE/71M6521FE ...
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... While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in zero state disabling both ADC and CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts. Figure 19 shows the functional blocks active in BROWNOUT mode. Page 101 71M6521DE/71M6521FE System Power Battery Power (Non-volatile Supply) MISSION ...
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... In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active. This mode can be exited only by system power-up, a timeout of the wake-up timer push button event. Figure 21 shows the functional blocks active in SLEEP mode. v1.0 71M6521DE/71M6521FE MISSION V3P3SYS falls ...
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... OPT_RXDIS OPT_RXINV WPULSE/ OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT WAKE V1 COMP_STAT Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out) Page 101 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 ...
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... MOD DIO2/ OPT_RXDIS WPULSE/ OPT_RXINV OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT WAKE V1 COMP_STAT Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out) v1.0 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 PLL ...
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... OPT_RXDIS WPULSE/ OPT_RXINV OPT_TXMOD OPT_TXE VARPULSE OPT_FDC OPT_TXINV VBIAS POWER FAULT WAKE V1 COMP_STAT Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out) Page 101 71M6521DE/71M6521FE VREF ΔΣ ADC CONVERTER VBIAS VBIAS - V3P3A + ADC_E VREF VREF FIR_LEN MCK DIV CK32 ...
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... V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together v1.0 71M6521DE/71M6521FE Transition MISSION 13..14 CK cycles Xtal 2048...4096 CK32 cycles BROWN- MISSION OUT Xtal 14.5 CK32 cycles 4096 CK32 ...
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... WAKE having been zero. The RTC clock will not be disturbed, but the MPU RAM must be re-initialized. The hardware watchdog timer will become active when the part enters MISSION mode. Page 101 71M6521DE/71M6521FE Xtal 14.5 CK32 cycles ...
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... Setting WAKE_ARM presets the timer with the values in WAKE_RES and WAKE_PRD and readies the timer to start when the MPU writes to SLEEP or LCD_ONLY. The timer is reset and disarmed whenever the MPU is awake. Thus desired to wake the MPU periodically (every 5 seconds, for example) the timer must be rearmed every time the MPU is awakened. v1.0 71M6521DE/71M6521FE Wake Up Behavior 15 CK32 cycles ...
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... SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals. VAR (DIO7) ADC Mux Ctrl. I/O RAM (CONFIGURATION RAM) Page 101 71M6521DE/71M6521FE Data Flow and V h for four-quadrant metering. These measurements are then accessed by the Pulses ...
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... Figure 28 and Figure 29 show how resistive dividers, current transformers, and restive shunts are connected to the voltage and current inputs of the 71M6521DE/FE Vin * R /(R out out Figure 28: Resistive Voltage Divider (Left), Current Transformer (Right) v1.0 71M6521DE/71M6521FE core + out out 1/N Vout = ...
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... Temperature Measurement − +25° read by the ADC by a 71M6521FE in the 64-pin LQFP n 449.648. 518,203, ⋅ − 512 ( 2220 ) Temperature Compensation 2 , respectively, the value of the VREF voltage (1.195V) has This means that PPMC = 26.84*TC1/1.195, and ⋅ ...
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... PPM deviations. A fairly close curve fit is achieved with the coefficients a = 10.89 0.122, and c = –0.00714 (see Figure 31). When applying the inverted coefficients, a curve (see Figure 31) will result that effectively neutralizes the original crystal characteristics. The frequencies were calculated using the fit coefficients as follows: v1.0 71M6521DE/71M6521FE Measured Nominal Frequency [Hz] +50 32767 ...
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... RTC. All digital input pins of the 71M6521DE/FE are compatible with external 5V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5V devices. Page 101 71M6521DE/71M6521FE crystal curve fit inverse curve ...
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... DIO19 to DIO4. DIO1 and DIO2 are always available, if not used for the optical port. Note that pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32 are not affected by LCD_NUM. Table 62 and Table 63 show the allocation of DIO and segment pins as a function of LCD_NUM for both package types. v1.0 71M6521DE/71M6521FE Connecting LCDs 6521 LCD ...
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... Note: LCD segment numbers are given without CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32. Table 62: LCD and DIO Pin Assignment by LCD_NUM for the QFN-68 Package Page 101 71M6521DE/71M6521FE Total Number of LCD Segment Pins DIO Pins in Addition Including SEG0- to DIO1-DIO2 SEG18 19 4-11,14-17, 19-21 20 ...
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... Pull-up resistors of roughly 10kΩ to V3P3D (to ensure operation in BROWNOUT mode) should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM must be set order to convert the DIO pins DIO4 and DIO5 to I and SDA v1.0 71M6521DE/71M6521FE Total Number of LCD DIO Pins in Addition Segment Pins In- ...
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... DIO pins DIO4 and DIO5 to uWire pins. The pull-up resistor for DIO5 may not be necessary. The RX pin should be pulled down by a 10kΩ resistor and additionally protected by a 100pF ceramic capacitor, as shown in Figure 35. Page 101 71M6521DE/71M6521FE Connecting Three-Wire EEPROMs 71M6521 71M6521 10kΩ ...
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... PCB necessary to have a provision like the header shown above R1 in Figure 37. A shorting jumper on this header pulls V3P3 disabling the hardware watchdog timer. The parallel impedance of R1 and R2 should be approximately 20 to 30kΩ in order to provide hysteresis for the power fault monitor. v1.0 71M6521DE/71M6521FE Optical Interface V3P3SYS V3P3SYS R ...
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... SECURE bit (SFR 0xB2[6]) set. Providing access to ICE_E ensures that the part can be reset between erase and program cycles, which will enable programming devices to reprogram the part. The reset required is im- plemented with a watchdog timer reset (i.e. the hardware WDT must be enabled). Page 101 71M6521DE/71M6521FE ...
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... Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented also possible to implement segment-wise calibration (depending on current range). The 71M6521DE/FE supports common industry standard calibration techniques, such as single-point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration. v1.0 71M6521DE/71M6521FE LCD Segments LCD Segments (optional) (optional) ...
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... Not Used LCD0 2030 … … LCD19 2043 LCD24 2048 … … LCD38 2056 LCD_BLNK 205A LCD_BLKMAP19[3:0] Page 101 71M6521DE/71M6521FE I/O RAM MAP – In Numerical Order Bit 5 Bit 4 Bit 3 CE_E SUM_CYCLES[5:0] CHOP_E[1:0] RTM_E Not Used Reserved CKOUT_E[1:0] VREF_DIS ECK_DIS FIR_LEN ADC_E ...
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... IFLAGS E8 IE_PLLRISE IE_WAKE WD_RST Flash: ERASE 94 FLSHCTL B2 PREBOOT SECURE PGADR B7 Serial EEPROM: EEDATA 9E EECTRL Only available on QFN-68 package. Reserved in LQFP-64 package. v1.0 71M6521DE/71M6521FE RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] Bit 5 Bit 4 Bit 3 Reserved Reserved DIO_DIR0[7:4] Reserved Reserved * DIO2[5:3] (QFN-68) DIO_DIR2[5:3] (QFN-68) INT5 ...
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... DIO_R8[2:0] 200D[6:4] DIO_R9[2:0] 200E[2:0] DIO_R10[2:0] 200E[6:4] DIO_R11[2:0] SFRA2 DIO_DIR0[7:4,2:1] [7:4,2:0] Page 101 71M6521DE/71M6521FE Wk Dir Description 0 0 R/W Enables ADC and VREF. When disabled, removes bias current 0 - R/W Battery Measure Enable. When set, a load current is immediately applied to the battery and it is connected to the ADC to be measured on Alternative Mux Cycles ...
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... EX_XFR 2002[1] EX_RTC 2007[4] EX_FWCOL 2007[5] EX_PLL 2005[4] FIR_LEN v1.0 71M6521DE/71M6521FE 0 0 R/W Programs the direction of pins DIO15-DIO14, DIO11-DIO8. 1 indi- cates output. Ignored if the pin is not configured as I/ Programs the direction of pins DIO17-DIO16 (and DIO19-DIO21 for R/W the QFN package). 1 indicates output. Ignored if the pin is not con- figured as I/O ...
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... IE_PLLFALL SFRE8[0] IE_XFER SFRE8[1] IE_RTC SFRE8[5] IE_WAKE Page 101 71M6521DE/71M6521FE Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. ...
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... LCD_SEG38[3:0] 2021[6] LCD_Y 2004[2:0] MPU_DIV[2:0] 2005[2] MUX_ALT 2002[7:6] MUX_DIV[1:0] v1.0 71M6521DE/71M6521FE -- -- R/W Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1 INT6. These bits do not have any memory and are primarily intended for debug use R/W Identifies which segments connected to SEG18 and SEG19 should blink. 1 means ‘ ...
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... RTC_MIN[5:0] 2017 RTC_HR[4:0] 2018 RTC_DAY[2:0] 2019 RTC_DATE[4:0] 201A RTC_MO[3:0] 201B RTC_YR[7:0] 201C[1] RTC_DEC_SEC 201C[0] RTC_INC_SEC 2002[3] RTM_E Page 101 71M6521DE/71M6521FE 0 0 R/W Selects OPT_TX modulation duty cycle OPT_FDC Function 00 50% Low 01 25% Low 10 12.5% Low 11 6.25% Low 0 0 R/W OPT_RX can be configured as an analog input to the optical UART comparator digital input/output, DIO1. 0— ...
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... VERSION[7:0] 2004[7] VREF_CAL 2004[3] VREF_DIS 20A9[7] WAKE_ARM 20A9[2:0] 001 WAKE_PRD 20A9[3] WAKE_RES v1.0 71M6521DE/71M6521FE 0 0 R/W Four RTM probes. Before each CE code pass, the values of these 0 0 registers are serially output on the RTM pin. The RTM registers are 0 0 ignored when RTM_E= ...
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... SFRE8[7] WD_RST 2002[2] WD_OVF 201F7:0] WE Page 101 71M6521DE/71M6521FE timer bit: Possible operations to this bit are: Read: Gets the status of the flag IE_PLLFALL Write 0: Clears the flag Write 1:.Resets the WDT 0 0 R/W The WD overflow status bit. This bit is set when the WD timer overflows ...
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... The required configuration is FIR_LEN = 1 (three cycles per conversion) and MUX_DIV = 1 (4 conversions per mux frame). v1.0 71M6521DE/71M6521FE CE Interface Description , where SAG_THR is the LSB value in the description of SAG_THR. ...
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... AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt). Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at every CE_BUSY interrupt. Page 101 71M6521DE/71M6521FE Element Input Mapping W0SUM/ W1SUM/ ...
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... MPU function. If EXT_PULSE = 1 and EQU = 0, the pulse inputs are W0SUM_X if I0SQSUM_X > I1SQSUM_X, and W1SUM_X, if I1SQSUM_X > I0SQSUM_X. Note: The 6521 Demo Code creep function halts both internal and external pulse generation. v1.0 71M6521DE/71M6521FE Default Description 0x5020 See description of CECONFIG below © ...
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... Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the integration time is 1 second. Additionally, the hardware will not permit output values to ‘fold back’ upon overflow. Page 101 71M6521DE/71M6521FE Default Description Number of consecutive voltage samples below SAG_THR before a sag 80 alarm is declared ...
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... MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X is the number of half- cycles accounted for in the last accumulated interval for the AC signal. TEMP_RAW may be used by the MPU to monitor chip temperature or to implement temperature compensation. v1.0 71M6521DE/71M6521FE -13 VMAX IMAX / In_8 Wh. -13 VMAX IMAX / In_8 Wh ...
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... RATE 46 2 where F = sampling frequency (2520.6Hz Pulse speed factor S Page 101 71M6521DE/71M6521FE Default Description The number of zero crossings of the selected voltage in the previous ac- N/A cumulation interval. Zero crossings are either direction and are debounced. N/A Filtered, unscaled reading from the temperature sensor. ...
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... QUANT_VARA 0x1B QUANT_VARB 0x16 QUANT_I v1.0 71M6521DE/71M6521FE CE Calibration Parameters Description These constants control the gain of their respective channels. The nominal value for each parameters is 2 proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow, CAL should be scaled by 1/(1 – 0.01). These two constants control the CT phase compensation. No compensation occurs when PHADJ_X = 0 ...
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... Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. Page 101 71M6521DE/71M6521FE ABSOLUTE MAXIMUM RATINGS © 2005-2008 TERIDIAN Semiconductor Corporation ...
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... VBAT Operating Temperature Maximum input voltage on DIO/SEG pins configured as DIO input. * *Exceeding this limit will distort the LCD waveforms on other pins. v1.0 71M6521DE/71M6521FE FUNCTION Bypass capacitor for 3.3V supply Bypass capacitor for 3.3V output Bypass capacitor for V3P3SYS Bypass capacitor for V2P5 32.768kHz crystal – electrically similar to ECS ...
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... Hysteresis Current V1 Response Time V1 WDT Disable Threshold (V1-V3P3A) BATTERY MONITOR BME=1 PARAMETER Load Resistor LSB Value - does not include the 9-bit left shift at CE input. Offset Error Page 101 71M6521DE/71M6521FE PERFORMANCE SPECIFICATIONS CONDITION VIN=0V, ICE_E=1 VIN=V3P3D CONDITION I = 1mA LOAD I = 15mA LOAD I ...
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... Voltage overhead V3P3-V2P5 PSSR ΔV2P5/ΔV3P3 LOW POWER VOLTAGE REGULATOR Unless otherwise specified, V3P3SYS=V3P3A=0, PB=GND (BROWNOUT) PARAMETER V2P5 V2P5 load regulation VBAT voltage requirement PSRR ΔV2P5/ΔVBAT v1.0 71M6521DE/71M6521FE CONDITION CONDITION | I | ≤ 1mA V3P3D | I | ≤ 1mA V3P3D CONDITION Reduce V3P3 until V2P5 ...
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... Applies to all COM and SEG pins. PARAMETER VLC2 Max Voltage VLC1 Voltage, 1/3 bias ½ bias VLC0 Voltage, 1/3 bias ½ bias VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes. Page 101 71M6521DE/71M6521FE CONDITION Crystal connected CONDITION Ta = 22ºC VREF_CAL = 10µA, -10µA LOAD = + − ...
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... LSB values do not include the 9-bit left shift at CE input. †† measured at T during meter calibration and is stored in MPU or CE for use in temperature calculations v1.0 71M6521DE/71M6521FE CONDITION Vin = 200mV peak, 65Hz Vcrosstalk = largest measurement Vin=65Hz, 64kpts FFT, Blackman- ...
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... This spec is measured in production at the limits of the specified operating temperature. 4 This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that use this nominal relationship as a reference. Page 101 71M6521DE/71M6521FE TIMING SPECIFICATIONS CONDITION CKMPU = 4.9MHz CKMPU = 1.25MHz ...
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... Harmonic Data - Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. Figure 41: Meter Accuracy over Harmonics at 240V, 30A v1.0 71M6521DE/71M6521FE 1 10 Current [A] 60Hz Harmonic Data Harmonic © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC ...
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... Figure 42: Typical Meter Accuracy over Temperature Relative to 25°C 11.7 12.3 PIN No. 1 Indicator 0.60 Typ. NOTE: Controlling dimensions are in mm Page 101 71M6521DE/71M6521FE Relative Accuracy over Temperature -40 - Temperature [°C] PACKAGE OUTLINE (LQFP 64) 11.7 12.3 9.8 10.2 0.14 0.50 Typ. 0.28 © 2005-2008 TERIDIAN Semiconductor Corporation ...
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... Pin length is nominally 0.4mm (min. 0.3mm, max 0.4mm) **) Exposed pad is internally connected to GNDD. v1.0 71M6521DE/71M6521FE PACKAGE OUTLINE (QFN 68) Symbol θ © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 Dimensions (in mm): Min. Nom. ...
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... COM1 COM2 COM3 Page 101 71M6521DE/71M6521FE PINOUT (LQFP-64) GNDD 1 ° SEG3 6 V3P3D 7 TERIDIAN 8 9 SEG4 71M6521FE-IGT 10 SEG5 11 12 COM0 13 COM1 14 COM2 15 16 COM3 PINOUT (QFN 68 TERIDIAN ...
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... Note 2: Soldering of bottom internal pad is not required for proper operation. Note 3: The ‘y’ dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the ‘G’ dimension is maintained. v1.0 71M6521DE/71M6521FE Recommended PCB Land Pattern Dimensions Description e ...
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... See the crystal manufacturer datasheet for details. Pin types Power Output Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”. Page 101 71M6521DE/71M6521FE PIN DESCRIPTIONS © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC ...
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... Pin types Power Output Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified on the following page. v1.0 71M6521DE/71M6521FE Description LCD common outputs: These 4 pins provide the select signals for the LCD display. Dedicated LCD segment output pins. Multi-use pins, configurable as either LCD SEG driver or DIO. (DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface, WPULSE = DIO6, VARPULSE = DIO7 when configured as pulse outputs) ...
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... CMOS Output Output Pin GNDD GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output Page: 100 of 101 71M6521DE/71M6521FE LCD SEG LCD Output Driver Pin GNDD LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG V3P3A ...
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... Tape & Reel 32KB Bulk 32KB Tape & Reel © 2005-2008 TERIDIAN Semiconductor Corporation Energy Meter IC DATASHEET JANUARY 2008 ORDERING PACKAGE NUMBER MARKING 71M6521DE-IGT/F 71M6521DE-IGT 71M6521DE-IGTR/F 71M6521DE-IGT 71M6521FE-IGT/F 71M6521FE-IGT 71M6521FE-IGTR/F 71M6521FE-IGT 71M6521DE-IM/F 71M6521DE-IM 71M6521DE-IMR/F 71M6521DE-IM 71M6521FE-IM/F 71M6521FE-IM 71M6521FE-IMR/F 71M6521FE-IM 1/18/2008 Page: 101 of 101 ...