wm8940gefl-v Wolfson Microelectronics plc, wm8940gefl-v Datasheet - Page 18

• Manufacturer Part Number: wm8940gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

WM8940
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INPUT SIGNAL PATH
MICROPHONE INPUTS
The WM8940 can accommodate a variety of microphone configurations including single ended and
differential inputs. The inputs through the MICN, MICP and optionally AUX pins are amplified through
the input PGA as shown in Figure 6 .
A pseudo differential input is the preferential configuration where the positive terminal of the input
PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground
should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when
AUX2INPPGA=1) input pins.
Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set
to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting
MICP2INPPGA to 0.
In pseudo-differential mode the larger signal should be input to MICP and the smaller (e.g. noisy
ground connections) should be input to MICN.
CONTROL INTERFACES
To allow full software control over all its features, the WM8940 supports 2 or 3 wire control interface.
It is fully compatible and an ideal partner for a wide range of industry standard microprocessors,
controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the
state of the MODE pin. If MODE is high then 3-wire control mode is selected, if MODE is low then 2-
wire control mode is selected.
In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8940 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to
the DAC/ADC.
However, a PLL is also included which may be used to generate the internal master clock frequency
in the event that this is not available from the system controller. This PLL uses an input clock,
typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not
required for generation of these clocks, it can be reconfigured to generate alternative clocks which
may then be output on the CLKOUT pin and used elsewhere in the system.
POWER CONTROL
The design of the WM8940 has given much attention to power consumption without compromising
performance. It operates at low supply voltages, and includes the facility to power off any unused
parts of the circuitry under software control.
As a power saving measure, ADC or DAC logic in the DSP core is held in its last enabled state when
the ADC or DAC is disabled. In order to prevent pops and clicks on restart due to residual data in
the filters, the master clock must remain for at least 64 input samples after the ADC or DAC has
been disabled.
The WM8940 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These
inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA
block which then feeds into a gain boost/mixer stage.
PD, Rev 4.2, April 2008
Production Data
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