wm8940gefl-v Wolfson Microelectronics plc, wm8940gefl-v Datasheet - Page 57

• Manufacturer Part Number: wm8940gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

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Production Data
Table 48 PLL Modes of Operation (Integer N mode)
INPUT CLOCK
11.2896MHz
12.2880MHz
(F
1
)
DESIRED PLL OUTPUT
INTEGER N DIVISION
FRACTIONAL K MODE
EXAMPLE:
The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12.
If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low
power operation.
The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up
to 1/2
division R, the fractional division K[23:0] and the integer division N[3:0] is:
K = 2
where 0 < (R – N) < 1 and K is rounded to the nearest whole number.
PLL input clock (f
R should be chosen to ensure 5 < N < 13. There is a fixed divide by 4 in the PLL and a selectable
divider (MCLKDIV[3:0]) after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
So N[3:0] will be 8h and K[23:0] will be 3126E9h to produce the desired 98.304MHz clock.
90.3168MHz
98.3040MHz
24
24
). If these are used then FRAC_EN must be set. The relationship between the required
( R – N)
(F
R = 98.304 / 12 = 8.192
N = int R = 8
K = int (2
2
)
1
) is 12MHz and the required clock (SYSCLK) is 12.288MHz.
24
x (8.192 – 8)) = 3221225 = 3126E9h
REQUIRED (R)
DIVISION
8
8
2
= 4 * 2 * 12.288MHz = 98.304MHz.
FRACTIONAL
DIVISION (K)
0
0
DIVISION (N)
INTEGER
8
8
PD, Rev 4.2, April 2008
WM8940
SDM
0
0
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