isppacclk5510v-01tn48i Lattice Semiconductor Corp., isppacclk5510v-01tn48i Datasheet
isppacclk5510v-01tn48i
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isppacclk5510v-01tn48i Summary of contents
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... Input Available only on ispClock 5520 © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor General Description and Overview The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5510 provides sin- gle-ended or five differential clock outputs, while ...
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Lattice Semiconductor Figure 2. ispClock5520 Functional Block Diagram PS0 PS1 Profile Select Control REFSEL REFA+ INPUT REFA- DIVIDER 0 M REFVTT (1-32) 1 REFB+ REFB- FEEDBACK N DIVIDER (1-32) JTAG INTERFACE TDI TMS LOCK RESET PLL_BYPASS ...
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Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage ...
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Lattice Semiconductor Performance Characteristics – Power Supply Symbol Parameter I Core Supply Current CCD I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG I/O Supply Current (static) CCJ 1. Supply current consumed by each ...
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Lattice Semiconductor DC Electrical Characteristics – Differential LVPECL Symbol Parameter V Input Voltage High IH V Input Voltage Low Output High Voltage Output Low Voltage OL 1. 100Ω differential termination. DC Electrical Characteristics – ...
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Lattice Semiconductor Switching Characteristics – Timing Adders for I/O Modes Adder Type Base Parameter( Input Adders IOI LVTTL_in LVCMOS18_in LVCMOS25_in LVCMOS33_in SSTL2_in SSTL3_in HSTL_in LVDS_in LVPECL_in Output Adders IOO LVTTL_out LVCMOS18_out LVCMOS25_out LVCMOS33_out SSTL2_out SSTL3_out ...
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Lattice Semiconductor Output Test Loads Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. Figure 3. CMOS Termination Load ispCLOCK ...
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Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance Output Resistance OUT 1. Guaranteed by characterization. Conditions V Voltage CCO Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω ...
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Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference input frequency f REF range t Reference input clock HIGH and CLOCKHI, t LOW times CLOCKLO t RINP, Input rise and fall times t FINP M M-divider range DIV N N-Divider ...
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Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter t Output-output Skew SKEW Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per range STEPS 2 t Skew Step Size SKSTEP t Skew Time Accuracy SKERR 1. ...
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Lattice Semiconductor Timing Specifications (Cont.) Boundary Scan Logic Symbol t TCK (BSCAN Test) Clock Cycle BTCP t TCK (BSCAN Test) Pulse Width High BTCH t TCK (BSCAN Test) Pulse Width Low BTCL t TCK (BSCAN Test) Setup Time BTSU t ...
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Lattice Semiconductor Timing Diagrams Figure 7. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 8. Programming Timing Diagram VIH ...
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Lattice Semiconductor Typical Performance Characteristics I vs. f CCD (Normalized to 640MHz) 1.2 1 0.8 0.6 0.4 0.2 0 300 400 500 f (MHz) VCO Typical Skew Error vs. Setting (Skew Mode = FINE, f 100 ...
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Lattice Semiconductor Typical Performance Characteristics (Cont.) Detailed Description PLL Subsystem The ispClock5500 provides an integrated phase-locked-loop (PLL) which may be used to generate output clock signals at lower, higher, or the same frequency as a user-supplied input reference signal. The ...
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Lattice Semiconductor above reasons recommended that when using phase-detect mode, the user wait a small amount of time (~25µs) between the time the LOCK signal is first asserted and the time at which the output clock signals are ...
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Lattice Semiconductor chosen to provide maximum loop stability while still providing exceptional jitter performance. Please note that when the skew mode is set to ‘coarse’, the effective value of NxV must be doubled. Refer to the section titled ‘Coarse Skew ...
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Lattice Semiconductor where f is the frequency of V divider the input reference frequency ref M and N are the input and feedback divider settings V is the setting of the V divider used to close ...
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Lattice Semiconductor Figure 13 shows the relative timing for a V-divider as a function of its 32 possible divisor settings (2-64) as the PLL locks. If two V-dividers are configured with the same divisor, their outputs will be synchronized. If ...
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Lattice Semiconductor Figure 14. Flipping Polarity to Edge Align Two Outputs Invert /8 Output Polarity / output /8 /16 For V-divider combinations in which one or more of the V-dividers is configured to a value that is not ...
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Lattice Semiconductor Clock reference inputs may be configured to interface to signals from the following logic families with little or no external support circuitry: • LVTTL (3.3V) • LVCMOS (1.8V, 2.5V, 3.3V) • SSTL2 • SSTL3 • HSTL • LVDS ...
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Lattice Semiconductor Figure 17. LVCMOS/LVTTL Input Receiver Configuration Signal In No Connect No Connect HSTL, SSTL2, SSTL3 The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input pair. ...
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Lattice Semiconductor Differential HSTL and SSTL HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory systems. Figure 19 shows how ispClock5500 reference input should be configured for accepting these standards. The major ...
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Lattice Semiconductor Note that while a floating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out- put driver ...
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Lattice Semiconductor In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ...
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Lattice Semiconductor ispClock5500’s internal termination resistors are not available in these modes. Also note that output slew-rate con- trol is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate. Polarity control (true/inverted) ...
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Lattice Semiconductor LVPECL mode. The far end of the transmission line must be terminated with a 100Ω resistor across the two signal lines. Figure 25. Configuration for LVDS and LVPECL Output Modes LVDS/LVPECL mode ispClock5500 Note that when in LVPECL ...
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Lattice Semiconductor Figure 26. Maximum Ambient Temperature vs. Number of Active Output Banks Temperature Derating Curves (Outputs LVCMOS 3.3V Active Output Banks Temperature Derating Curves (Outputs LVDS ...
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Lattice Semiconductor • GOE – global output enable • OEX, OEY – secondary output enable controls • SGATE – synchronous output control 2 Additionally, internal E CMOS configuration bits are provided for the purpose of modifying the effects of these ...
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Lattice Semiconductor grammed by the user over a range 15. The ispClock5500 family also supports both ‘fine’ and ‘coarse’ skew modes. In fine skew mode, the unit skew ranges from 195ps to 390 ps, while in the ...
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Lattice Semiconductor When one moves from coarse skew mode to fine skew mode, the extra divide-by-two factor is removed from between the VCO and the V-divider bank, halving the VCO’s effective operating frequency. To compensate for this change, all of ...
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Lattice Semiconductor Figure 29. Output Timing Adders for Logic Type (a) and Output Slew Rate (b) LVPECL Output ( IOS LVTTL Output (T = 0.1ns) IOS Similarly, when one changes the slew rate of an output, the output ...
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Lattice Semiconductor – Signal Inversion • V-Divider to be used as feedback source • Internal feedback delay compensation • Fine/Coarse skew mode selection • UES string If any of the above items are modified, the change will apply across all ...
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Lattice Semiconductor Figure 30. PAC-Designer Design Entry Screen (ispClock5520) In-System Programming The ispClock5500 is an In-System Programmable (ISP™) device. This is accomplished by integrating all E configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial ...
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Lattice Semiconductor Figure 31. Download from a PC PAC-Designer Software ispClock5500 Family Data Sheet Other System Circuitry ispDownload Cable (6') 4 ispClock5500 Device 35 ...
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Lattice Semiconductor IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispClock5500 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispClock5500 both as a serial programming interface, and for boundary ...
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Lattice Semiconductor Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by ...
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Lattice Semiconductor facturer to determine. The instruction word length is not mandated other than minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- ...
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Lattice Semiconductor type and version code (Figure 34). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device issuing a Test-Logic-Reset instruction. The bit code for this instruction is ...
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Lattice Semiconductor VERIFY – This instruction loads data from the E shifted out. The device must already be in programming mode for this instruction to execute. VERIFY_INCR – This instruction copies the E umn register and then auto-increments the value ...
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Lattice Semiconductor Pin Descriptions Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘5’ VCC VCCO_6 Output Driver ...
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Lattice Semiconductor Pin Descriptions (Continued) Pin Name Description VCCD Digital Core VCC GNDD Digital GND VCCJ JTAG interface VCC REFA+ Clock Reference A positive input REFA- Clock Reference A negative input REFB+ Clock Reference B positive input REFB- Clock Reference ...
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Lattice Semiconductor VCCA, GNDA – These pins provide analog supply and ground for the ispClock5500 family’s internal analog cir- cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu- ...
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Lattice Semiconductor Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0. SECTION NOTES: 1. DIMENSIONING ...
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Lattice Semiconductor 100-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR TOP VIEW SIDE VIEW SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 ...
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Lattice Semiconductor Part Number Description ispPAC-CLK55XX XXXX X Device Family Device Number CLK5510 CLK5520 Ordering Information Conventional Packaging Part Number ispPAC-CLK5510V-01T48C ispPAC-CLK5520V-01T100C Part Number ispPAC-CLK5510V-01T48I ispPAC-CLK5520V-01T100I Lead-Free Packaging Part Number ispPAC-CLK5510V-01TN48C ispPAC-CLK5520V-01TN100C Part Number ispPAC-CLK5510V-01TN48I ispPAC-CLK5520V-01TN100I Commercial ...
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Lattice Semiconductor Package Options ispClock5510: 48-pin TQFP VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 ispClock5500 Family Data Sheet ispPAC CLK5510V-01T48C ...
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Lattice Semiconductor ispClock5520: 100-pin TQFP n/c 1 n/c 2 VCCO_0 3 BANK_0B 4 BANK_0A 5 GNDO_0 6 VCCO_1 7 BANK_1B 8 BANK_1A 9 GNDO_1 10 VCCO_2 11 BANK_2B 12 BANK_2A 13 GNDO_2 14 VCCO_3 15 BANK_3B 16 BANK_3A 17 GNDO_3 ...