pex8525-aa25bi PLX, pex8525-aa25bi Datasheet
pex8525-aa25bi
Manufacturer Part Number
pex8525-aa25bi
Description
Pex 8525 24 Lane, 5 Port Pci Express Switch, 31 X 31mm? Pbga
Manufacturer
PLX
Datasheet
1.PEX8525-AA25BI.pdf
(4 pages)
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Features
o 24-lane PCI Express switch
o Up to five configurable ports
o 31mm x31mm,
o Typical Power: 2.6 Watts
o Standard Compliant
o High Performance
o Flexible Configuration
o PCI Express Power Management
o Quality of Service (QoS)
o Reliability, Availability, Serviceability
PEX 8525 General Features
PEX 8525 Key Features
- Integrated SerDes
(x1, x2, x4, x8, x16)
644-ball PBGA package
- PCI Express Base Specification, r1.0a
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 115ns max
- Five highly flexible & configurable
- Configurable with strapping pins,
- Lane and polarity reversal
- Link power management states: L0,
- Device states: D0 and D3hot
- One Virtual Channel per port
- Eight Traffic Classes per port
- Weighted Round-Robin Ingress Port
- 3 Standard Hot-Plug Controllers
- Upstream port as hot-plug client
- Transaction Layer end-to-end CRC
- Poison bit
- INTA# interrupt signal
- Fatal Error (FATAL_ERR#) signal
- PCIe baseline error reporting
- Advanced Error Reporting
- Port Status bits and GPO available
- Per port error diagnostics
- JTAG boundary scan
packet latency (x8 to x8)
ports (x1, x2, x4, x8, or x16)
EEPROM, I
L0s, L1, L2/L3 Ready, and L3
Arbitration
(legacy SERR equivalent)
• Bad DLLPs
• Bad TLPs
• CRC errors
Version 1.5 2008
2
C, or Host software
Multi-purpose, High Performance ExpressLane™ Switch
The ExpressLane PEX 8525 device offers PCI Express switching capability
enabling users to add scalable high bandwidth, non-blocking interconnection
to a wide variety of applications including servers, storage systems,
communications platforms, blade servers, and embedded-control
products. The PEX 8525 is well suited for fan-out, aggregation, dual-
graphics, peer-to-peer, and intelligent I/O module applications.
Highly Flexible Port Configurations
The PEX 8525 offers highly configurable ports. There are a maximum of 5
ports that can be configured to any legal width from x1 to x16, in any
combination to support your specific bandwidth needs. The ports can be
configured for symmetric (each port having the same lane width and traffic
load) or asymmetric (ports having different lane widths) traffic. In the event
of asymmetric traffic, the PEX 8525 features a flexible central packet
memory that allocates a memory buffer for each port as required by the
application or endpoint. This buffer allocation along with the device's
flexible packet flow control minimizes bottlenecks when the upstream and
aggregated downstream bandwidths do not match (are asymmetric). Any of
the ports can be designated as the upstream port, which can be changed
dynamically.
High Performance
The PEX 8525 architecture supports packet cut-thru with a max latency of
115ns (x8 to x8). This, combined with large packet memory (1024 byte
maximum payload size) and non-blocking internal switch architecture,
provide full line rate on all ports for performance-hungry applications such as
storage servers or storage switch fabrics.
End-to-end Packet Integrity
The PEX 8525 provides end-to-end CRC protection (ECRC) and Poison bit
support to enable designs that require end-to-end data integrity. These
features are optional in the PCI Express specification, but PLX provides
them across its entire ExpressLane switch product line.
Configuration Flexibility
The PEX 8525 provides several ways to configure its operations. The device
can be configured through strapping pins, I
cycles, or an optional serial EEPROM. This allows for easy debug during the
development phase, performance monitoring during the operation phase, and
driver or software upgrade.
Interoperability
The PEX 8525 is designed to be fully compliant with the PCI-SIG revision
1.1 specification. Additionally, it supports auto-negotiation, lane reversal,
and polarity reversal. The PEX 8525 also undergoes thorough
Interoperability testing in PLX’s Interoperability Lab.
High-Performance 24-lane, 5-port PCIe Switch
PLX Confidential
PEX 8525
2
C interface, CPU configuration
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pex8525-aa25bi Summary of contents
Page 1
... The PEX 8525 provides end-to-end CRC protection (ECRC) and Poison bit support to enable designs that require end-to-end data integrity. These features are optional in the PCI Express specification, but PLX provides them across its entire ExpressLane switch product line. Configuration Flexibility The PEX 8525 provides several ways to configure its operations ...
Page 2
... SerDes Power and Signal Management The PEX 8525 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power – off, low, typical, and high. The SerDes block also supports loop-back modes ...
Page 3
... The PEX 8525 enables designers to take, for example, two x8 PCIe ports and expand them into eight downstream ports. Some of these PCIe ports can be bridged to PCI or PCI-X using bridging products from PLX. Figure 7 illustrates one of the many configurations the PEX 8525 can support. Host Host ...
Page 4
... Product Ordering Information PLX Technology, Inc. 870 Maude Ave. Part Number Sunnyvale, CA 94085 USA PEX8525-AA25BI Tel: 1-800-759-3735 PEX8525-AA25BI G Tel: 1-408-774-9060 PEX 8525-AA RDK Fax: 1-408-774-2169 Please visit the PLX Web site at Email: info@plxtech.com Web Site: www.plxtech.com © 2008 PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc ...