Features
o 27 x 27mm
o Typical Power: 3.8 Watts
o Standards Compliant
o High Performance
o Flexible Configuration
o Quality of Service (QoS)
o Reliability, Availability, Serviceability
PEX 8647 General Features
PEX 8647 Key Features
- 48-lane, 3-port PCIe Gen 2 switch
- PCI Express Base Specification, r2.0
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 140ns max packet
- 2KB Max Payload Size
- Read Pacing (bandwidth throttling)
- Dual Cast
- Registers configurable with strapping
- Lane and polarity reversal
- Selectable upstream port
- Compatible with PCIe 1.0a PM
- Eight traffic classes per port
- Weighted round-robin source
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- INTA# and FATAL_ERR# signals
- Advanced Error Reporting
- Port Status bits and GPIO available
- Per port error diagnostics
- Performance Monitoring
-
Integrated 5.0 GT/s SerDes
(backwards compatible w/ PCIe r1.0a/1.1)
latency (x16 to x16)
pins, EEPROM, I
port arbitration
• Per port payload & header counters
JTAG AC/DC boundary scan
Version 0.95 2008
2
, 676-pin FCBGA package
2
C, or host software
The ExpressLane
capability enabling users to add scalable high bandwidth, non-blocking
interconnection to high-end graphics applications. The PEX 8647 is
optimized to support high-resolution graphics while supporting peer-to-peer
traffic and Dual Cast for maximum performance.
High Performance & Low Packet Latency
The PEX 8647 architecture supports packet cut-thru with a maximum
latency of 140ns (x16 to x16). This, combined with large packet memory
and non-blocking internal switch architecture, provides full line rate on all
ports for performance-hungry graphics applications. The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput. Flexible buffer
allocation, along with the device's flexible packet flow control, maximizes
throughput for graphics applications where more traffic flows in the
downstream, rather than upstream, direction.
Data Integrity
The PEX 8647 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction as packets
pass through the switch.
Register Configuration Flexibility
The PEX 8647 provides several ways to configure its operations. The device
can be configured through strapping pins, I
cycles, or an optional serial EEPROM. This allows for easy debug during the
development phase, performance monitoring during the operation phase, and
driver or software upgrade.
Dual Cast™
The PEX 8647 supports Dual Cast, a feature which allows for the copying of
data (e.g. packets) from one ingress port to two egress ports allowing for
higher performance in dual-graphics applications.
Read Pacing™
The Read Pacing feature allows users to throttle the amount of read requests
being made by downstream devices. When a downstream device requests
several long reads back-to-back, the Root Complex gets tied up in serving
this downstream port. If this port has a narrow link and is therefore slow in
receiving these read packets from the Root Complex, then other downstream
ports may become starved – thus, impacting performance. The Read Pacing
feature enhances, under user control, system performance by allowing for the
adequate servicing of all downstream devices.
PCIe Gen 2, 5.0GT/s 48-lane, 3-port PCIe Switch
PEX 8647
TM
PEX 8647 device offers PCI Express switching
2
C interface, CPU configuration