a3pn010 Actel Corporation, a3pn010 Datasheet - Page 78

• Manufacturer Part Number: a3pn010
• Description: Proasic 3 Nano Flash Fpgas
• Manufacturer: Actel Corporation

Radiation-Tolerant ProASIC3 FPGAs
Table 2-112 • Input Data Register Propagation Delays
Table 2-113 • Input Data Register Propagation Delays
2 -6 6
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
For specific junction temperature and voltage supply levels, refer to
values.
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
Timing Characteristics
Military-Case Conditions: T
Military-Case Conditions: T
J
J
= 125°C, Worst-Case V
= 125°C, V
Description
Description
A d v a n c e v 0. 1
CC
= 1.425 V
CC
= 1.14 V
Table 2-5 on page 2-8
Table 2-5 on page 2-8
0.33 0.39
0.36 0.43
0.00 0.00
0.51 0.60
0.00 0.00
0.63 0.74
0.63 0.74
0.00 0.00
0.31 0.36
0.00 0.00
0.31 0.36
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
0.25 0.30
0.28 0.33
0.00 0.00
0.39 0.46
0.00 0.00
0.48 0.56
0.48 0.56
0.00 0.00
0.24 0.28
0.00 0.00
0.24 0.28
0.19 0.22
0.19 0.22
0.31 0.36
0.28 0.32
–1
–1
for derating
for derating
Std. Units
Std. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns