ht82m9aae Holtek Semiconductor Inc., ht82m9aae Datasheet

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ht82m9aae

Manufacturer Part Number
ht82m9aae
Description
Usb Mouse Encoder 8-bit Mcu With Eeprom
Manufacturer
Holtek Semiconductor Inc.
Datasheet
Technical Document
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Features
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General Description
The USB MCU OTP body is suitable for USB mouse
and USB joystick devices. It consists of a Holtek high
performance 8-bit MCU core for control unit, built-in
USB SIE, 4K´15 ROM and 224 bytes data RAM.
The mask version HT82M9AAE is fully pin and function-
ally compatible with the OTP version HT82M9AEE device.
Rev. 1.20
Tools Information
FAQs
Application Note
Flexible total solution for applications that combine
PS/2 and low-speed USB interface, such as mice,
joysticks, and many others
USB Specification Compliance
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Supports 1 low-speed USB control endpoint and
2 interrupt endpoint
Each endpoint has 8´8 bytes FIFO
Integrated USB transceiver
3.3V regulator output
External 6MHz or 12MHz ceramic resonator or crystal
8-bit RISC microcontroller, with 4K´15 program
224 bytes RAM (20H~FFH)
memory (000H~FFFH)
Conforms to USB specification V1.1
Conforms to USB HID specification V1.1
USB Mouse Encoder 8-Bit MCU with EEPROM
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There are two dice in the HT82M9AEE/HT82M9AAE
package: one is the HT82M9AE/HT82M9AA MCU, the
other is a 128´8 bits EEPROM used for data memory
purpose. The two dice are wrie-bonded to from
HT82M9AEE/HT82M9AAE.
128´8 data EEPROM
6MHz/12MHz internal CPU clock
4-level stacks
Two 8-bit indirect addressing registers
One 16-bit programmable timer counter with
overflow interrupt (shared with PA7, vector 0CH)
One USB interrupt input (vector 04H)
HALT function and wake-up feature reduce power
consumption
PA0~PA7, PB4/SDA and PB7/SCL support wake-up
function
Internal Power-On reset (POR)
Watchdog Timer (WDT)
16 I/O ports
20/24-pin SOP package
HT82M9AEE/HT82M9AAE
August 13, 2007

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ht82m9aae Summary of contents

Page 1

... USB joystick devices. It consists of a Holtek high performance 8-bit MCU core for control unit, built-in USB SIE, 4K´15 ROM and 224 bytes data RAM. The mask version HT82M9AAE is fully pin and function- ally compatible with the OTP version HT82M9AEE device. Rev. 1.20 HT82M9AEE/HT82M9AAE · ...

Page 2

... Block Diagram Pin Assignment Rev. 1.20 HT82M9AEE/HT82M9AAE August 13, 2007 ...

Page 3

... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.20 HT82M9AEE/HT82M9AAE Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register) ...

Page 4

... System Start-up Timer Period SST t Crystal Setup OSC Note: Power-on period WDT SST OSC WDT Time-out in normal mode=1/f RCSYS WDT Time-out in HALT mode=1/f RCSYS Rev. 1.20 HT82M9AEE/HT82M9AAE Test Conditions Min. V Conditions DD ¾ ¾ 3.3 ¾ No load, f =6MHz 5V SYS ¾ load, system HALT, USB suspend ¾ ...

Page 5

... SCL Pins) t Write Cycle Time WR Note: These parameters are periodically sampled but not 100% tested * The standard mode means V =2.2V to 5.5V CC For relative timing, refer to timing diagrams Rev. 1.20 HT82M9AEE/HT82M9AAE Standard Mode* Remark Min. Max. ¾ ¾ 100 ¾ ¾ 4000 ¾ ...

Page 6

... S11 S10 Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.20 HT82M9AEE/HT82M9AAE After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. ...

Page 7

... Note: *11~*0: Table location bits @7~@0: TBLP bits Rev. 1.20 HT82M9AEE/HT82M9AAE ROM data by two table read instructions: ²TABRDC² and ²TABRDL², transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows: The instructions ² ...

Page 8

... The RAM bank 1 mapping is as shown. Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.20 HT82M9AEE/HT82M9AAE Bank 0 RAM Mapping Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...

Page 9

... Bank 1 RAM Mapping Rev. 1.20 HT82M9AEE/HT82M9AAE Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions ...

Page 10

... HT82M9AEE/HT82M9AAE receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82M9AEE/HT82M9AAE is set and a USB interrupt is also triggered. Function INTC (0BH) Register ...

Page 11

... When the HT82M9AEE/HT82M9AAE receives a Re- sume signal from the Host PC, the resume line (bit3 of the USC) of the HT82M9AEE/HT82M9AAE are set and a USB interrupt is triggered. Whenever a USB reset signal is detected, the USB in- terrupt is triggered and URST_Flag bit of the USC regis- ter is set. When the interrupt has been served, the bit should be cleared by firmware ...

Page 12

... The WDT and WDT prescaler will be cleared and re- counted again (if the WDT clock is from the WDT os- cillator). Rev. 1.20 HT82M9AEE/HT82M9AAE Watchdog Timer · All of the I/O ports remain in their original status. · The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig- nal on port WDT overflow ...

Page 13

... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. Reset Timing Chart Rev. 1.20 HT82M9AEE/HT82M9AAE The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable ...

Page 14

... SCC 0000 0000 uu00 u000 Note: ²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown² Rev. 1.20 HT82M9AEE/HT82M9AAE RES Reset WDT RES Reset USB-Reset (Normal Time-Out (HALT) Operation) ...

Page 15

... TM1 11=Pulse width measurement mode 00=Unused Rev. 1.20 HT82M9AEE/HT82M9AAE nal (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the f (Timer). The pulse width measurement mode can be used to count the high or low level duration of the exter- nal signal (TMR) ...

Page 16

... To function as an input, the corresponding latch Rev. 1.20 HT82M9AEE/HT82M9AAE of the control register must write a ²1². The input source also depends on the control register. If the control regis- ter bit is ²1², the input will read the pad state. If the con- trol register bit is ² ...

Page 17

... Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.20 HT82M9AEE/HT82M9AAE The relationship between must ...

Page 18

... After a read sequence, the stop command will place the EEPROM in a standby power mode (re- fer to Start and Stop Definition Timing Diagram). Rev. 1.20 HT82M9AEE/HT82M9AAE · Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has re- ceived each word ...

Page 19

... ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received. Acknowledge Polling Flow Rev. 1.20 HT82M9AEE/HT82M9AAE · Read operations The data EEPROM supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to ² ...

Page 20

... ACK² signal (high) followed by a stop condition. Data EEPROM Timing Diagrams Note: The write cycle time t is the time from a valid stop condition of a write sequence to the end of the valid start WR condition of sequential command. Rev. 1.20 HT82M9AEE/HT82M9AAE Sequential Read Timing 20 August 13, 2007 ...

Page 21

... Register Register R/W Name Address Pipe_ctrl R/W 01000001B STALL R/W 01000011B Endpt_EN R/W 01000111B Pipe_ctrl (41H), STALL (43H) and Endpt_EN (47H) Registers Rev. 1.20 HT82M9AEE/HT82M9AAE SIES MISC Endpt_EN FIFO 0 45H 46H 47H 48H Register Memory Mapping Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Address value Default value=00000000 Bit7~Bit3 ...

Page 22

... End of transient flag, normal status is ²1². If suspend=²1² line & EOT=²0² indicates that EOT R something is wrong in the USB Interface. The programmer must do something to save the device and keep it alive. MNI R/W This bit is for masking the NAK interrupt when MNI=²1², the default value=²0² Rev. 1.20 HT82M9AEE/HT82M9AAE Read/Write R R/W R/W ...

Page 23

... FIFO pointer register (FIFO0, FIFO1, FIFO2). The following are two examples for reading and writing the FIFO data: HT82M9AEE/HT82M9AAE FIFO is read by packet. To read from FIFO, the following should be followed: · Select one set of FIFO, set in the read mode (MISC TX bit = 0), and set the REQ bit to ² ...

Page 24

... When the resume signal is sent out by the host, the HT82M9AEE/HT82M9AAE will wake-up the MCU by USB interrupt and the Resume line (bit 3 of the USC) is set. In order to make the HT82M9AEE/HT82M9AAE function properly, the programmer must set the USBCKEN (bit 3 of the SCC and clear the SUSP2 (bit4 of the SCC) ...

Page 25

... PS2DAI, the PS2DAO should be set to ²1². Oth- erwise it always read a ²0² HT82M9AAE is defined as a USB interface. Both the USBD- and USBD+ are driven by the USB SIE of the HT82M9AEE/HT82M9AAE. User only writes or reads the USB data through the corresponding FIFO. Both SPS2 and SUSB default is ² ...

Page 26

... PEC6 R/W 7 PEC7 R/W USB_flag Rev. 1.20 HT82M9AEE/HT82M9AAE Functions USB suspend mode status bit. When 1, indicates that the USB system entry is in suspend mode. When RESUME_OUT EVENT, RESUME_O is set to ²1². The default value is ²0². USBD-/DATA input USBD+/CLK input Output for driving USBD-/DATA pin, when working under 3D PS2 mouse function. The default value is ² ...

Page 27

... TBHP enable/disable (default: disable output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Rev. 1.20 HT82M9AEE/HT82M9AAE Functions ¾ Reserved, must set to ²0². USB clock control bit. When set to ²1², indicates a USBCK ON, else USBCK OFF. The default value is ²0². This bit is used to reduce power consumption in the suspend mode. In the normal mode this bit must be cleared to zero(De- fault=² ...

Page 28

... X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.20 HT82M9AEE/HT82M9AAE ...

Page 29

... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.20 HT82M9AEE/HT82M9AAE Instruction Description 29 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...

Page 30

... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the ²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ²ROM code TBHP option² is enabled (6) : ²ROM code TBHP option² is disabled Rev. 1.20 HT82M9AEE/HT82M9AAE Instruction Description 30 Flag Cycle Affected 2 ...

Page 31

... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ¬ ACC+[m] Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE Ö Ö Ö Ö Ö ...

Page 32

... Affected flag(s) TO PDF ¾ ¾ CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. [m] ¬ 00H Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ Ö ¾ ¾ ¾ Ö ¾ ¾ ...

Page 33

... CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] ¬ [m] Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ ¾ ¾ ...

Page 34

... Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. ACC ¬ [m]-1 Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ Ö ¾ ¾ ¾ ...

Page 35

... PDF ¾ ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. ACC ¬ [m] Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ ¾ ¾ Ö ¾ ...

Page 36

... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ¬ACC ²OR² [m] Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ ¾ ¾ ...

Page 37

... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) Operation ACC.0 ¬ [m].7 Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ ¾ ...

Page 38

... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) Operation [m].7 ¬ ¬ [m].0 Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ Ö ¾ ...

Page 39

... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ¬ ([m]-1) Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ Ö ...

Page 40

... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i¹0 Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ ¾ ...

Page 41

... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 ¬ [m].7~[m].4 Operation ACC.7~ACC.4 ¬ [m].3~[m].0 Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE Ö Ö Ö Ö ...

Page 42

... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ¬ ROM code (low byte) Operation TBLH ¬ ROM code (high byte) Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ ¾ ...

Page 43

... Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. ACC ¬ ACC ²XOR² x Operation Affected flag(s) TO PDF ¾ ¾ Rev. 1.20 HT82M9AEE/HT82M9AAE ¾ ¾ ¾ ¾ ¾ ...

Page 44

... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 C 14 490 C¢ ¾ 0° Rev. 1.20 HT82M9AEE/HT82M9AAE a Dimensions in mil Nom. Max. ¾ 419 ¾ 300 ¾ 20 ¾ 510 ¾ 104 ¾ 50 ¾ ¾ ¾ 38 ¾ 12 ¾ 10° ...

Page 45

... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 C 14 590 C¢ ¾ 0° Rev. 1.20 HT82M9AEE/HT82M9AAE a Dimensions in mil Nom. Max. ¾ 419 ¾ 300 ¾ 20 ¾ 614 ¾ 104 ¾ 50 ¾ ¾ ¾ 38 ¾ 12 ¾ 10° ...

Page 46

... Space Between Flange T2 Reel Thickness SOP 24W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.20 HT82M9AEE/HT82M9AAE Dimensions in mm 330±1 62±1.5 13+0.5 -0.2 2±0.5 24.8+0.3 -0.2 30.2±0.2 Dimensions in mm 330±1 62±1.5 13+0.5 -0.2 2±0.5 24.8+0.3 -0.2 30.2±0.2 ...

Page 47

... D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.20 HT82M9AEE/HT82M9AAE Dimensions in mm 24+0.3 -0.1 12±0.1 1.75±0.1 11.5±0.1 1.5+0.1 1.5+0.25 4±0.1 2±0.1 10.8±0.1 13.3±0.1 3.2±0.1 0.3±0.05 21.3 Dimensions in mm 24±0.3 12±0.1 1.75±0.1 11.5± ...

Page 48

... Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 HT82M9AEE/HT82M9AAE 48 August 13, 2007 ...

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