ht82k74e Holtek Semiconductor Inc., ht82k74e Datasheet
ht82k74e
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ht82k74e Summary of contents
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... SSOP, 32-pin QFN and 48-pin SSOP/LQFP packages HT82K74EE: 28-pin SSOP and 48-pin SSOP/LQFP packages There are two dice in the HT82K74EE package: one is the HT82K74E MCU, the other is a 128 8 bits EEPROM used for data memory purpose. The two dice are wire-bonded to form HT82K74EE 1 /8, f ...
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... Pin Assignment Rev. 1.00 HT82K74E/HT82K74EE 2 December 15, 2009 ...
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... PE0~PE3 I/O Wake-up put. Configuration options determine if the pins have pull-high resistors. For HT82K74EE PE0 and PE1 are shared with the SDA and SCL lines respec- tively and not bonded to external pins. OSC1 I OSC1, OSC2 are connected to an external 27MHz crystal/ resonator for the in- ...
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... System Start-up Timer Period SST t Crystal Setup OSTSETUP t Low Voltage Width to Reset LVR t External Reset Low Pulse Width RES Note: t =1/f SYS SYS Rev. 1.00 HT82K74E/HT82K74EE Test Conditions Min. V Conditions DD Others 2.0 f =27MHz 2.8 SYS 3V No load 27MHz SYS No load, system HALT WDT disable, LVR disable 0 0 ...
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... VDD Rise Rate to Ensure Power-on RSR_ POR Reset Maximum VDD Start Voltage to V POR_MAX Ensure Power-on Reset t Power-on Reset Low Pulse Width POR Rev. 1.00 HT82K74E/HT82K74EE Test Conditions Min. V Conditions DD PWRAMP option selected Half PWRAMP option selected Full Test Conditions Min. V Conditions DD 2 ...
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... Note: These parameters are periodically sampled but not 100% tested * The standard mode means V ** For related timing, refer to timing diagrams in the EEPROM Data Memory section Rev. 1.00 HT82K74E/HT82K74EE Remark After this period the first clock pulse is generated Only relevant for repeated START condition ...
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... Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and Rev. 1.00 HT82K74E/HT82K74EE execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive in- ...
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... PCL bits #10~#0: Instruction code address bits S10~S0: Stack register bits Rev. 1.00 HT82K74E/HT82K74EE After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited ...
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... After a device reset is initiated, the program will jump to this location and begin execu- tion. Rev. 1.00 HT82K74E/HT82K74EE Location 008H This vector is used by the timer/event counter counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full ...
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... Program Memory of device. The table pointer is setup here to have an initial value of 06H . This will ensure that the first data read from the data ta- Table Read - TBLP only Rev. 1.00 HT82K74E/HT82K74EE Table Location Bits ...
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... As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.00 HT82K74E/HT82K74EE 11 December 15, 2009 ...
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... Data Memory. Rev. 1.00 HT82K74E/HT82K74EE Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and ...
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... The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad- dresses. Rev. 1.00 HT82K74E/HT82K74EE stead of the usual direct memory addressing method where the actual memory address is defined. Any ac- tions on the IAR register will result in corresponding read/write operations to the memory location specified by the Memory Pointer MP ...
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... Once TBHP is enabled, the in- struction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Rev. 1.00 HT82K74E/HT82K74EE Otherwise, the TBHP function selected via a configura- tion option is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits ...
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... Memory table, which are used to transfer the appropri- ate output or input data on that port. With each I/O port Rev. 1.00 HT82K74E/HT82K74EE there is an associated control register labeled PAC, PBC, PCC, PDC, PEC also mapped to specific ad- dresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs ...
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... If the comparison of the device address is successful then the EEPROM will output a zero as an ACK bit. If not, the EEPROM will return to a standby state. Rev. 1.00 HT82K74E/HT82K74EE Write Operations Byte write A write operation requires an 8-bit data word address following the device address word and acknowledg- ment ...
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... The microcontroller should respond with a No ACK signal - high - followed by a stop condition. Refer to Random read timing. Rev. 1.00 HT82K74E/HT82K74EE Sequential read Sequential reads are initiated by either a current ad- dress read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment ...
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... Port Pin Wake-up If the HALT instruction is executed, the device will enter the Power Down Mode, where the system clock will stop Rev. 1.00 HT82K74E/HT82K74EE resulting in power being conserved, a feature that is im- portant for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low or low to high ...
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... The ZA/ZB is for Z-axis function The ZA/ZB pins are shared with the PD2/PD3, PD2 or Rev. 1.00 HT82K74E/HT82K74EE Input/Output Ports PD3 has falling and rising edge wake-up function if its wake-up function is enabled by related configuration option. In halt mode if PD2 wakes up the MCU, the bit6 named ZA_wakeup in the Wake-up Status Regis- ter WSR will be set ...
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... Timer/Event Counter Structure Rev. 1.00 HT82K74E/HT82K74EE An external clock source is used when the timer is in the event counting mode, the clock source being provided on shared pin PA2/TMR. Depending upon the condition of the TE bit, each high to low, or low to high transition on the PA2/TMR pin will increment the counter by one ...
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... TON or bit 4 of the TMRC register provides the basic Timer/Event Counter Control Register Rev. 1.00 HT82K74E/HT82K74EE on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the TE or bit 3 of the TMRC register ...
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... PA2/TMR pin, the timer will Pulse Width Measure Mode Timing Chart Rev. 1.00 HT82K74E/HT82K74EE start counting until the PA2/TMR pin returns to its origi- nal high level. At this point the TON bit will be automati- cally reset to zero and the timer will stop counting. If the ...
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... Rev. 1.00 HT82K74E/HT82K74EE When the Timer/Event Counter is read data is writ- ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer ...
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... The Program Counter will then be loaded with a new address which will be the value of the correspond- Rev. 1.00 HT82K74E/HT82K74EE ing interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruc- tion at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine ...
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... By disabling the interrupt enable bit, the requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this Rev. 1.00 HT82K74E/HT82K74EE condition in the interrupt control register until the corre- sponding interrupt is serviced or until the request flag is cleared by a software instruction. ...
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... RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be Rev. 1.00 HT82K74E/HT82K74EE inhibited. After the RES line reaches a certain voltage value, the reset delay time t is invoked to provide ...
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... SST WDT Time-out Reset during Power Down Timing Chart Rev. 1.00 HT82K74E/HT82K74EE Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer ...
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... RFCTR 0000 0000 PTR 0000 0000 TBHP 0000 0000 Note: * means warm reset - not implemented u means unchanged x means unknown Rev. 1.00 HT82K74E/HT82K74EE RES Reset (Normal Operation) 000H 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu ...
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... All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to Rev. 1.00 HT82K74E/HT82K74EE an extremely low standby current level. This occurs be- cause when the device enters the Power Down Mode, the system oscillator is stopped which reduces the ...
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... HALT instruction, this will be executed immediately after the 512 system clock period delay has ended. Rev. 1.00 HT82K74E/HT82K74EE Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown lo- cations, due to certain uncontrollable external events such as electrical noise ...
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... VA_wakeup 4 PF4 VB_wakeup 5 PF5 CNT_WK 6 PF6 ZA_wakeup 7 PF7 ZB_wakeup Rev. 1.00 HT82K74E/HT82K74EE Watchdog Timer Register Watchdog Timer Register R/W Description for mouse mode Always read change before default 1: VB change before default 1: MCU wake-up by period counter overflow R 0: MCU Wake-up not by period counter ...
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... R/W 6 OSC2_C2 R/W 7 OSC2_C3 R/W Where X is 3pf capacitor. OSC CAP Control Register - OSCC Rev. 1.00 HT82K74E/HT82K74EE R/W Description for Mouse Mode Control AMP function R AMP function 0: off AMP function (default) This bit is used to decide whether the DC/DC circuit is in operation R/W 0: enable the DC/DC circuit 0: disable the DC/DC circuit Flag for 2 ...
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... R/W Name 0~7 Period Timer R/W Rev. 1.00 HT82K74E/HT82K74EE Description for mouse mode DD Description The Period Timer is the time interval generator with one second as a unit. If the bits [7:0] are equal to 00H, the MCU will be woken up by one of the wake-up source mentioned in Wake-up Section except the PTR overflow event ...
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... The I/O port output delay time of the rising and falling transition is 100ns or 200ns. There is a configuration op- tion bit to define the slew rate of all I/O pins. Rev. 1.00 HT82K74E/HT82K74EE Amplifier Output for 27MHz The RF_OUT pin is the signal output pin and is sourced from the system oscillator clock output signal via a power amplifier ...
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... PD0~PD7 pull-high by nibble: pull-high or non-pull-high 9 PE0~PE3 wake-up by nibble: wake-up or non-wake-up 10 PE0~PE3 pull-high by nibble: pull-high or non-pull-high 11 WDT: enable or disable 12 TBHP function: enable or disable 13 DC-DC output voltage: 2.8V, 3.0V, 3.3V 14 LVR: enable or disable 15 LVD voltage: 2.2V or 2.0V 16 I/O Slew Rate: 100ns or 200ns 17 Power Amp: full or half Application Circuits Rev. 1.00 HT82K74E/HT82K74EE Options 35 December 15, 2009 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT82K74E/HT82K74EE subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT82K74E/HT82K74EE Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT82K74E/HT82K74EE Description 38 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 HT82K74E/HT82K74EE 39 December 15, 2009 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 HT82K74E/HT82K74EE addr 40 December 15, 2009 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1.00 HT82K74E/HT82K74EE December 15, 2009 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 HT82K74E/HT82K74EE addr 42 December 15, 2009 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 HT82K74E/HT82K74EE Stack Stack Stack [m]. 0~6) 43 December 15, 2009 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 HT82K74E/HT82K74EE [m]. 0~6) 44 December 15, 2009 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 HT82K74E/HT82K74EE [ December 15, 2009 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 HT82K74E/HT82K74EE 0 [m] [ December 15, 2009 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 HT82K74E/HT82K74EE [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 47 December 15, 2009 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 HT82K74E/HT82K74EE 48 December 15, 2009 ...
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... Package Information 28-pin SSOP (150mil) Outline Dimensions Symbol Rev. 1.00 HT82K74E/HT82K74EE Dimensions in mil Min. Nom. 228 150 8 386 Max. 244 157 12 394 December 15, 2009 ...
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... SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions Symbol Symbol Rev. 1.00 HT82K74E/HT82K74EE Dimensions in inch Min. Nom. 0.028 0.000 0.008 0.007 0.197 0.197 0.020 0.049 0.049 0.012 Dimensions in mm Min. Nom. 0.70 0.00 0.20 0.18 5.00 5.00 0.50 1.25 1.25 0.30 50 Max. ...
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... SSOP (300mil) Outline Dimensions Symbol Symbol Rev. 1.00 HT82K74E/HT82K74EE Dimensions in inch Min. Nom. 0.395 0.291 0.008 0.613 0.085 0.025 0.004 0.025 0.004 0 Dimensions in mm Min. Nom. 10.03 7.39 0.20 15.57 2.16 0.64 0.10 0.64 0. Max. 0.420 0.299 0.012 0.637 0.099 ...
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... LQFP (7mm´7mm) Outline Dimensions Symbol Rev. 1.00 HT82K74E/HT82K74EE Dimensions in mm Min. Nom. 8.90 6.90 8.90 6.90 0.50 0.20 1.35 0.10 0.45 0. Max. 9.10 7.10 9.10 7.10 1.45 1.60 0.75 0.20 7 December 15, 2009 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 HT82K74E/HT82K74EE Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330.0 1.0 100.0 0.1 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 32.2 38.2 0.2 53 December 15, 2009 ...
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... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT82K74E/HT82K74EE Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 54 December 15, 2009 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT82K74E/HT82K74EE Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.10 14.2 0.1 2 Min. +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 12.0 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 0.1 55 December 15, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT82K74E/HT82K74EE 56 December 15, 2009 ...