ht82k95e Holtek Semiconductor Inc., ht82k95e Datasheet
ht82k95e
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ht82k95e Summary of contents
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... Bit manipulation instruction 15-bit table read instruction 63 powerful instructions All instructions in one or two machine cycles 28-pin SOP, 32-pin QFN, 48-pin SSOP package power consumption. The mask version HT82K95A is fully pin and functionally compatible with the OTP ver- sion HT82K95E device. 1 April 16, 2008 ...
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... Block Diagram Rev. 2.00 HT82K95E/HT82K95A 2 April 16, 2008 ...
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... RES I VDD V33O O USBD+/CLK I/O Rev. 2.00 HT82K95E/HT82K95A Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register). Pull-high resistor options: PA0~PA7 CMOS/NMOS/PMOS options: PA0~PA7 Wake up options: PA0~PA7 PA6 and PA7 are pin-shared with TMR0 and TMR1 input, respectively ...
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... V 3.3V Regulator Output V33O C Build_in Capacitance in OSC1 OSC1 Rev. 2.00 HT82K95E/HT82K95A Description USBD- or PS2 DATA I/O line USB or PS2 function is controlled by software control register OSC1, OSC2 are connected to a 6MHz or 12MHz Crystal/resonator (determined by software instructions) for the internal system clock. +6.0V Storage Temperature ............................ 125 ...
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... Watchdog Time-out Period (WDT OSC) WDT1 t Watchdog Time-out Period (System Clock) WDT2 t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT Rev. 2.00 HT82K95E/HT82K95A Test Conditions Min. Typ. V Conditions Test Conditions Min. Typ. Max. V Conditions ...
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... Return from subroutine S11 Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 2.00 HT82K95E/HT82K95A incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call or return ...
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... Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 2.00 HT82K95E/HT82K95A Location 00CH This location is reserved for the Timer/Event Counter 1 interrupt service program timer interrupt results from a Timer/Event Counter 1 overflow, and the inter- rupt is enabled and the stack is not full, the program begins execution at location 00CH ...
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... TBHP;1FH), table higher-order (STATUS;0AH), interrupt control register (INTC;0BH), Rev. 2.00 HT82K95E/HT82K95A Bank 0 RAM Mapping Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H), I/O control registers (PAC ...
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... set by a WDT time-out. 6~7 Unused bit, read as 0 Rev. 2.00 HT82K95E/HT82K95A Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator ...
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... USC) of the HT82K95E/HT82K95A is set and a USB interrupt is also triggered. Also when the HT82K95E/HT82K95A receives a Re- sume signal from the Host PC, the resume line (bit3 of the USC) of HT82K95E/HT82K95A is set and a USB in- terrupt is triggered. Whenever a USB reset signal is detected, the USB in- terrupt is triggered. ...
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... This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an exter- nal signal to conserve power. Rev. 2.00 HT82K95E/HT82K95A A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of ...
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... RES reset during normal operation 0 0 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an 12 HT82K95E/HT82K95A SYS RESET Conditions April 16, 2008 ...
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... PC 1111 1111 1111 1111 PCC 1111 1111 1111 1111 PD 1111 1111 1111 1111 Rev. 2.00 HT82K95E/HT82K95A Reset Configuration The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear Clear. After master reset, WDT WDT begins counting ...
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... To enable/disable timer 1 counting (0=disabled; 1=enabled) To define the operating mode 01=Event count mode (external clock) 6 TM0 10=Timer mode (internal clock) 7 TM1 11=Pulse width measurement mode 00=Unused Rev. 2.00 HT82K95E/HT82K95A RES Reset WDT RES Reset (Normal Time-Out (HALT) Operation) (HALT)* 1111 1111 1111 1111 ...
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... The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting en- able or disable and active edge. Rev. 2.00 HT82K95E/HT82K95A Timer/Event Counter 0 Timer/Event Counter 1 The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0/TMR1) pin ...
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... Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output Rev. 2.00 HT82K95E/HT82K95A or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under soft- ware control. To function as an input, the corresponding latch of the control register must write a 1 ...
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... SUSP2 (bit4 of the SCC USB mode set this bit LVR OPT must disable When the resume signal is sent out by the host, the HT82K95E/HT82K95A will wake up the MCU by USB in- terrupt and the Resume line (bit 3 of the USC) is set. In order to make the HT82K95E/HT82K95A function prop- erly, the firmware must set the USBCKEN (bit 3 of the SCC and clear the SUSP2 (bit4 of the SCC) ...
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... If SPS2=0, and SUSB=1, the HT82K95E/HT82K95A is configured as a USB interface. Both the USBD- and USBD+ is driven by the SIE of the HT82K95E/ HT82K95A. User can only write or read the USB data through the corresponding FIFO. Both SPS2 and SUSB default ...
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... PC Host IN or OUT token. Only for Endpoint0 1: has only USB interrupt, data is transmitted to the PC host or data is received from NMI R/W the PC Host 0: always has USB interrupt if the USB accesses FIFO0 Default 0 Rev. 2.00 HT82K95E/HT82K95A Bit7~Bit3 Reserved Bit 2 Pipe 2 Pipe 2 Pipe 2 Pipe 2 Bit5 ...
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... Check whether FIFO0 can be read or not Check whether FIFO1 can be written or not Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence to FIFO1 Note: *: There are 2 s existing between 2 reading action or between 2 writing action Rev. 2.00 HT82K95E/HT82K95A Function MISC (46H) Register Bank Address 1 ...
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... R/W The USB function is selected when this bit is set (Default This flag is used to show the MCU is in USB mode. (Bit=1) 7 USB_flag R/W This bit is R and will be cleared to 0 after power-on reset. (Default Rev. 2.00 HT82K95E/HT82K95A Function USC (1AH) Register Function USR (1BH) Register 21 April 16, 2008 ...
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... PA0~PA7 wake-up enabled or disabled (by bit) 12 PB0~PB7 wake-up enabled or disabled (by nibble) 13 PC0~PC7 wake-up enabled or disabled (by nibble) 14 PD0~PD7 wake-up enabled or disabled (by nibble) 15 TBHP enable or disable (default disable) Rev. 2.00 HT82K95E/HT82K95A Function SCC (1CH) Register Read/Write Option R Store current table read bit11~bit8 data Option 22 Functions ...
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... Application Circuits Crystal or Ceramic Resonator for Multiple I/O Applications for HT82K95E Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible. ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 2.00 HT82K95E/HT82K95A subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 2.00 HT82K95E/HT82K95A Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 2.00 HT82K95E/HT82K95A Description 26 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 2.00 HT82K95E/HT82K95A 27 April 16, 2008 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 2.00 HT82K95E/HT82K95A addr 28 April 16, 2008 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 2. HT82K95E/HT82K95A April 16, 2008 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 2.00 HT82K95E/HT82K95A addr 30 April 16, 2008 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 2.00 Stack Stack Stack [m]. 0~6) 31 HT82K95E/HT82K95A April 16, 2008 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 2.00 [m]. 0~6) 32 HT82K95E/HT82K95A April 16, 2008 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 2.00 [ HT82K95E/HT82K95A April 16, 2008 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 2.00 0 [m] [ HT82K95E/HT82K95A April 16, 2008 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 2.00 HT82K95E/HT82K95A [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 35 April 16, 2008 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 2.00 HT82K95E/HT82K95A 36 April 16, 2008 ...
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... Package Information 28-pin SOP (300mil) Outline Dimensions Symbol Rev. 2.00 Dimensions in mil Min. Nom. 394 290 14 697 HT82K95E/HT82K95A Max. 419 300 20 713 104 April 16, 2008 ...
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... SAW Type QFN Outline Dimensions Symbol Rev. 2.00 Dimensions in mm. Min. Nom. 0.7 0 0.2 0. 0.5 1.25 1.25 0.3 38 HT82K95E/HT82K95A Max. 0.8 0.05 0.3 3.25 3.25 0.5 April 16, 2008 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 2.00 Dimensions in mil Min. Nom. 395 291 8 613 HT82K95E/HT82K95A Max. 420 299 12 637 April 16, 2008 ...
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... Space Between Flange T2 Reel Thickness SAW QFN 32 (5 5mm) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 HT82K95E/HT82K95A Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 12.5+0.3 0.2 40 April 16, 2008 ...
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... SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 HT82K95E/HT82K95A Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 41 April 16, 2008 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 HT82K95E/HT82K95A Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 Dimensions 0.3 8 0.1 1.75 0.1 5.5 0.05 1.5+0.1 1.5+0.25 4 0.1 2 0.05 5.25 0.1 5.25 0.1 1 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 HT82K95E/HT82K95A Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 43 April 16, 2008 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.00 HT82K95E/HT82K95A 44 April 16, 2008 ...