gal16v8d-10qp Lattice Semiconductor Corp., gal16v8d-10qp Datasheet

gal16v8d-10qp

Manufacturer Part Number

gal16v8d-10qp

Description

Gal Data Sheets High Performance E2 Cmos Pld Generic Array Logic?

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL16V8D-10QP.pdf (24 pages)

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• HIGH PERFORMANCE E

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

• ACTIVE PULL-UPS ON ALL PINS

• E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

The GAL16V8, at 3.5 ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configura-

tions possible with the GAL16V8 are the PAL architectures listed

in the table of the macrocell description section. GAL16V8 devices

are capable of emulating any of these PAL architectures with full

function/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

16v8_11

Features

Description

— 3.5 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3.0 ns Maximum from Clock Input to Data Output

— UltraMOS

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 20-pin PAL

— 100% Functional Testability

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

CELL TECHNOLOGY

Function/Fuse Map/Parametric Compatibility

) floating gate technology to provide the highest speed

Advanced CMOS Technology

CMOS

Devices with Full

TECHNOLOGY

I/CLK

Functional Block Diagram

Pin Configuration

I/CLK

GND

GAL16V8

GND

Top View

PLCC

SOIC

16V8

GAL

View

Top

I/CLK

I/OE

High Performance E

I/O/Q

Vcc

I/O/Q

Vcc

I/O/Q

I/OE

I/O/Q

Generic Array Logic™

GAL16V8

I/CLK

GND

CLK

OLMC

16V8

CMOS PLD

GAL

August 2006

DIP

I/O/Q

I/OE

Vcc

I/O/Q

I/OE

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