gal16v8d-10lr-883 Lattice Semiconductor Corp., gal16v8d-10lr-883 Datasheet

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gal16v8d-10lr-883

Manufacturer Part Number
gal16v8d-10lr-883
Description
High Performance E2 Cmos Pld Generic Array Logic?
Manufacturer
Lattice Semiconductor Corp.
Datasheet
• HIGH PERFORMANCE E
• 50% REDUCTION IN POWER FROM BIPOLAR
• ACTIVE PULL-UPS ON ALL PINS (GAL16V8D-7 and
• E
• EIGHT OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL16V8/883 is a high performance E
mable logic device processed in full compliance to MIL-STD-883.
This military grade device combines a high performance CMOS
process with Electrically Erasable (E
provide the highest speed/power performance available in the
883 qualified PLD market. The GAL16V8D/883, at 7.5ns maxi-
mum propagation delay time, is the world's fastest military quali-
fied CMOS PLD.
The generic GAL architecture provides maximum design flexibil-
ity by allowing the Output Logic Macrocell (OLMC) to be config-
ured by the user. The GAL16V8/883 is capable of emulating all
standard 20-pin PAL
metric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are specified.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16v8mil_03
Features
Description
— 7.5 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 6 ns Maximum from Clock Input to Data Output
— TTL Compatible 12 mA Outputs
— UltraMOS
— 75mA Typ Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 20-pin PAL
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
GAL16V8D-10)
2
CELL TECHNOLOGY
Fuse Map/Parametric Compatibility
®
Advanced CMOS Technology
®
devices with full function/fuse map/para-
2
CMOS
®
Devices with Full Function/
®
2
) floating gate technology to
TECHNOLOGY
2
CMOS program-
1
I/CLK
Functional Block Diagram
Pin Configuration
I
I
I
I
I
I
I
I
I
I
I
I
I
6
8
4
3
I
9
I
GAL16V8
GND
Top View
2
I
LCC
I/CLK
I/OE
11
I/O/Q
Vcc
High Performance E
20
I/O/Q
GAL16V8/883
I/O/Q
19
13
16
18
14
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
I/CLK
GND
8
8
8
8
8
8
8
8
CLK
I
I
I
I
I
I
I
I
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
5
1
10
CERDIP
16V8
February 1999
GAL
2
OE
CMOS PLD
20
11
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE

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gal16v8d-10lr-883 Summary of contents

Page 1

... Electrically Erasable ( floating gate technology to provide the highest speed/power performance available in the 883 qualified PLD market. The GAL16V8D/883, at 7.5ns maxi- mum propagation delay time, is the world's fastest military quali- fied CMOS PLD. The generic GAL architecture provides maximum design flexibil- ity by allowing the Output Logic Macrocell (OLMC config- ured by the user ...

Page 2

... The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL16V8D-7/10/883 Recommended Operating Conditions (1) Case Temperature (T +1 ...

Page 3

... Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL16V8D-7/10/883 Over Recommended Operating Conditions MAXIMUM* UNITS -10 MIN. MAX. MIN. MAX. 1 7.5 2 ...

Page 4

... Supply Current f toggle 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL16V8D/883 Recommended Operating Conditions (1) Case Temperature (T +1.0V Supply voltage ( ...

Page 5

... Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL16V8D/883 Over Recommended Operating Conditions MAXIMUM* UNITS -15 -20 -30 MIN. MAX. MIN. MAX. MIN. MAX. 3 ...

Page 6

Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL16V8/883 INPUT or I/O FEEDBACK ...

Page 7

Descriptions LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC REGISTER ARRAY max with No Feedback Note: ...

Page 8

... Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recom- mended. Part Number Description GAL16V8D Device Name Speed (ns Low Power Power Specifications GAL16V8/883 ...

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