gal20xv10 Lattice Semiconductor Corp., gal20xv10 Datasheet

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gal20xv10

Manufacturer Part Number
gal20xv10
Description
High-speed E2 Cmos Pld Generic Array Logic?
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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• HIGH PERFORMANCE E
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
• ACTIVE PULL-UPS ON ALL PINS
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20xv10_02
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counter-
parts. E
times providing the ability to reprogram, reconfigure or test the de-
vices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configu-
rations possible with the GAL20XV10 are the PAL
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Features
Description
— 10 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 90mA Maximum Icc
— 75mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with
— Registered or Combinatorial with Polarity
— High Speed Counters
— Graphics Processing
— Comparators
2
CELL TECHNOLOGY
PAL12L10, 20L10, 20X10, 20X8, 20X4
2
CMOS technology offers high speed (<100ms) erase
®
Advanced CMOS Technology
2
2
) floating gate technology to provide
CMOS
®
TECHNOLOGY
®
architectures
1
Functional Block Diagram
Pin Configuration
NC
I
I
I
I
I
I
11
5
7
9
12
4
GAL20XV10
I/CLK
I/OE
Top View
PLCC
I
I
I
I
I
I
I
I
I
I
14
2
28
16
26
18
21
25
23
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
High-Speed E
GAL20XV10
Generic Array Logic™
I/CLK
GND
4
4
4
4
4
4
4
4
4
4
I
I
I
I
I
I
I
I
I
I
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
1
6
12
20XV10
2
GAL
DIP
CMOS PLD
July 1997
18
13
24
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
I/O/Q
I/O/Q
I/O/Q

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gal20xv10 Summary of contents

Page 1

... Exclusive-OR PLD available in the market. At 90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides a substantial savings in power when compared to bipolar counter- parts CMOS technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the de- vices quickly and efficiently ...

Page 2

... GAL20XV10 Ordering Information Commercial Grade Specifications Part Number Description GAL20XV10B Device Name Speed (ns Low Power Power Specifications GAL20XV10 ...

Page 3

... I/CLK pin used as the register clock and the I/OE pin as an output enable for all registers. The following is a list of PAL archi- tectures that the GAL20XV10 can emulate. It also shows the global architecture mode used to emulate the PAL architecture. PAL Architectures Emulated by ...

Page 4

... Input Mode OE CLK XOR CLK OE XOR Specifications GAL20XV10 XOR Registered Configuration - SYN = 1. - AC0 = 0. - AC1 = OLMC 1 and OLMC10 do not have the Q - Pin 1(2) can be CLK and/or Input. - Pin 13(16) can be OE and/or Input. Registered Configuration - SYN = 1. - AC0 = 1. - AC1 = 0. - XOR = 1 defines Active Low Output. ...

Page 5

... ELECTRONIC SIGNATURE FUSES 1631, 1632, .... Byte4 Byte3 .... Specifications GAL20XV10 DIP (PLCC) Package Pinouts .... 1669, 1670 .... Byte1 Byte0 5 OLMC 23(27) XOR - 1600 AC0 - 1610 AC1 - 1620 OLMC ...

Page 6

... Feedback Mode OE CLK XOR CLK OE XOR Specifications GAL20XV10 XOR Registered Configuration - SYN = 0. - AC0 = AC1 = Dedicated CLK input on Pin 1(2). - Dedicated OE input on Pin 13(16). Registered Configuration - SYN = 0. - AC0 = 1. - AC1 = XOR = 1 defines Active Low Output. - XOR = 0 defines Active High Output Dedicated CLK input on Pin 1(2). ...

Page 7

... ELECTRONIC SIGNATURE FUSES 1631, 1632, .... Byte4 Byte3 .... Specifications GAL20XV10 DIP (PLCC) Package Pinouts .... 1669, 1670 .... Byte1 Byte0 7 OLMC 23(27) XOR - 1600 AC0 - 1610 AC1 - 1620 OLMC ...

Page 8

... The leakage current is due to the internal pull-up on all input and I/O pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 3) Typical values are and T CC Specifications GAL20XV10 Recommended Operating Conditions (1) Commercial Devices: Ambient Temperature ( +1.0V ...

Page 9

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested Specifications GAL20XV10 Over Recommended Operating Conditions COM MIN. MAX — 76.9 100 100 4 4 ...

Page 10

... Clock Width Input/Output Equivalent Schematics PIN (Vref Typical = 3.2V) Active Pull-up Circuit Vcc Vref ESD Protection Circuit PIN ESD Protection Circuit Typical Input Specifications GAL20XV10 INPUT or I/O FEEDBACK t pd CLK REGISTERED OUTPUT OUTPUT CLK REGISTERED FEEDBACK Vcc Vcc 10 VALID INPUT ...

Page 11

... Active High B Active Low 300 Active High C Active Low 300 Specifications GAL20XV10 su+ co) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above ...

Page 12

... NOTE: The electronic signature bits, if programmed to any value other then zero(0) will alter the checksum of the device. Security Cell A security cell is provided in every GAL20XV10 device as a deter- rent to unauthorized copying of the device pattern. Once pro- grammed, this cell prevents further read access of the device pattern information ...

Page 13

... Temperature (deg. C) Delta Tpd Outputs 0 -0 Number of Outputs Switching Delta Tpd vs Output Loading 12 10 RISE 8 FALL 100 Output Loading (pF) Specifications GAL20XV10 Normalized Tco vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 Supply Voltage (V) Normalized Tco vs Temp 1.3 RISE 1.2 FALL 1.1 1 0.9 0.8 0.7 -55 - Temperature (deg ...

Page 14

... Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications GAL20XV10 Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 5.50 -55 - Temperature (deg. C) Input Clamp (Vik 100 120 -2 ...

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