m52d32321a Elite Semiconductor Memory Technology Inc., m52d32321a Datasheet
m52d32321a
Related parts for m52d32321a
m52d32321a Summary of contents
Page 1
... PIN CONFIGURATION (TOP VIEW) Elite Semiconductor Memory Technology Inc. Mobile Synchronous DRAM GENERAL DESCRIPTION The M52D32321A is 33,554,432 bits synchronous high data rate Dynamic RAM organized 524,288 words by 32 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
Page 2
... Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. M52D32321A LWE LDQM 512K x 32 512K x 32 ...
Page 3
... I - -10 OL ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ ° 1MHz) Symbol C CLK ADD C OUT M52D32321A Value -1.0 ~ 2.6 -1.0 ~ 2.6 - 150 0.7 50 ° C ° Typ Max Unit 1.8 1.9 V 1.8 V +0.3 V DDQ 0 0 ...
Page 4
... CLK V (max Input signals are stable I = 0mA, Page Burst OL All Band Activated (min) CCD CCD ≥ (min) RFC RFC TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52D32321A ° Version -7 - 0.3 ∞ = 0.2 =15ns 3 ∞ 1.5 ∞ =15ns 10 ∞ = 2.5 70 ...
Page 5
... CDL t (min) RDL t (min) BDL t (min) CCD t (max) REF CAS latency=3 CAS latency=2 after self refresh exit. RFC M52D32321A ° ° ) Value / 0.2 DDQ 0 DDQ 0 DDQ See Fig.2 Vtt =0.5x VDDQ Output Z0=50 (Fig.2) AC Output Load Circuit Version -10 ...
Page 6
... Symbol Min Max 7 t 1000 SAC - SLZ - 6 t SHZ - 9 *All AC parameters are measured from half to half. M52D32321A -10 Unit Note Min Max 9 1000 ...
Page 7
... Reserved Reserved Reserved Reserved Reserved M52D32321A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...
Page 8
... ATCSR 0 0 Elite Semiconductor Memory Technology Inc TCSR PASR DS ATCSR M52D32321A A0 Address bus Extended Mode Register A2-0 Self Refresh Coverage 000 Full Array 001 1/2 of Full Array 010 1/4 of Full Array PASR 011 Reserved 100 Reserved 101 Reserved 110 ...
Page 9
... M52D32321A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...
Page 10
... Entry Exit Entry Exit (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) after the end of burst. RP M52D32321A DQM BA A10/AP A9~A0 Note RAS CAS ...
Page 11
... *Note M52D32321A *Note2,3 *Note4 *Note2 *Note 3 *Note4 ...
Page 12
... Enable auto precharge, precharge bank A at end of burst Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation M52D32321A Publication Date : May 2009 Revision : 1.6 12/30 ...
Page 13
... Elite Semiconductor Memory Technology Inc M52D32321A ...
Page 14
... Qa2 Qa0 Qa1 Qa3 Qa0 Qa1 Qa2 Qa3 Row Active Precharge (A-Bank) ) after the clock. SHZ +CAS latency-1)+t RCD M52D32321A Cb0 Rb Db0 Db1 Db2 *Note4 Db2 Db0 Db1 *Note4 (A- (A-Ban k) ...
Page 15
... HIGH Cb0 Qa0 Qb0 Qb1 Qb2 Qa1 Qa1 Qb0 Qb1 Qa0 *Note1 Read (A-Bank) before Row precharge, will be written. RDL M52D32321A *Note2 Cc0 Cd0 t RDL Dc0 Dc1 Dd1 Dd0 Dc0 Dc1 Dd0 Dd2 t CDL *Note3 ...
Page 16
... HIGH RBb CBb RBb QAa0 QAa1 QAa2 QAa3 QBb0 QAa0 QAa1 QAa3 QAa2 Read (B-Bank) Row Active (B-Bank) M52D32321A CAc CBd CAe QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QBb1 QBb0 QBb2 QBb3 QAc0 QAc1 QBd0 ...
Page 17
... Elite Semiconductor Memory Technology Inc HIGH CBb RBb RBb DBb2 DBb3 DAa1 DAa2 DAa3 DBb0 DBb1 t CDL Write (B-Bank) (B-Bank) M52D32321A *Note2 CAc CBd DAc0 DAc1 DBd0 DBd1 t RDL *Note1 Precharge Write (Both Banks) (A-Bank) Write ...
Page 18
... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note: 1.t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52D32321A Publication Date : May 2009 Revision : 1.6 18/30 ...
Page 19
... Read with Auto Precharge Auto Precharge Start Point ( A - Bank ) ( A - Bank) before internal precharge start RAS M52D32321A ...
Page 20
... Elite Semiconductor Memory Technology Inc M52D32321A ...
Page 21
... *Note2 M52D32321A ...
Page 22
... Elite Semiconductor Memory Technology Inc M52D32321A ...
Page 23
... Row Active (B-Bank) Read with Auto Precharge (A-Bank) M52D32321A * ...
Page 24
... Row Active Precharge Active Power-Down Power-down Exit Entry M52D32321A Read Active Power-down Exit Publication Date : May 2009 Revision : 1 ...
Page 25
... Elite Semiconductor Memory Technology Inc *Note3 RAS M52D32321A ...
Page 26
... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M52D32321A ...
Page 27
... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc M52D32321A Publication Date : May 2009 Revision : 1.6 27/30 ...
Page 28
... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Min Norm Max Min 1.00 0.30 0.35 0.40 0.012 0.586 0.40 0.45 0.50 0.016 7.90 8.00 8.10 0.311 12.90 13.00 13.10 0.508 6.40 11.20 0.80 M52D32321A Dimension in inch Norm Max 0.039 0.014 0.016 0.023 0.018 0.020 0.315 0.319 0.512 0.516 0.252 0.441 0.031 Publication Date : May 2009 Revision : 1.6 28/30 ...
Page 29
... Upgrade the specification of speed grade - 7 instead of -7.5 6. Add the description about A9 bit of MRS 1. Add the specification Correct the voltage of absolute maximum ratings 2009.05.04 3. Correct L(U)DQM to DQM0~3 4. Correct Power Up Sequence for EMRS and add the chart of EMRS M52D32321A Description REF RFC Publication Date : May 2009 Revision : 1.6 29/30 ...
Page 30
... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52D32321A Publication Date : May 2009 Revision : 1.6 30/30 ...