m52s128168a Elite Semiconductor Memory Technology Inc., m52s128168a Datasheet
m52s128168a
Related parts for m52s128168a
m52s128168a Summary of contents
Page 1
... GENERAL DESCRIPTION The M52S128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized 2,097,152 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications ...
Page 2
... Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. M52S128168A Bank D Bank C Bank B Bank A ...
Page 3
... ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ = 25 C ° 1MHZ) SYMBOL C IN1 C IN2 C OUT M52S128168A VALUE -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 ° MAX UNIT 2 +0.3 V DDQ 0 0.2 V μ μ ...
Page 4
... V (min), CLK V (max Input signals are stable I = 0mA, Page Burst OL All Band Activated, tCCD = tCCD (min) ≥ (min TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52S128168A Version -7 -7.5 80 0.5 ∞ = 0.5 =10ns 10 ∞ ∞ =15ns 25 ∞ 150 ...
Page 5
... RC t (min) RFC t (min) CDL t (min) RDL t (min) BDL t (min) CCD t (min) MRD CAS latency=3 CAS latency=2 t (max) REF after self refresh exit. RFC M52S128168A Unit / 0 DDQ ns V DDQ Version Unit -7 -7.5 - ...
Page 6
... SAC 7 t 2.5 2 2.5 2 2.5 2 SLZ 5.5 t SHZ 7 *All AC parameters are measured from half to half. M52S128168A -7.5 -10 Unit Max Min Max 10 1000 1000 2 2 Publication Date: Dec. 2008 Revision: 1 ...
Page 7
... X X Exit Entry Exit Valid , X = Don’t Care Logic High , L = Logic Low ) M52S128168A DQM BA0 WE A10/AP A9~A0 BA1 CODE Row Address L Column ...
Page 8
... Reserved Reserved Reserved Reserved Reserved Reserved M52S128168A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...
Page 9
... If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored has +/-5°C tolerance Elite Semiconductor Memory Technology Inc PASR DS M52S128168A Address bus Extended Mode Register Set A2-A0 Self Refresh Coverage 000 4Bank 001 2 Bank (BankA& BankB) or (BA1=0) PASR 010 1 Bank (BankA) or ...
Page 10
... M52S128168A Interleave Interleave ...
Page 11
... CS high. CS high disables the command decoder so that RAS , CAS , WE and all the address inputs are ignored. Elite Semiconductor Memory Technology Inc. M52S128168A MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the ...
Page 12
... Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. M52S128168A after the last data input to RDL is defined as the minimum number of clock RP ...
Page 13
... NOP’s for a minimum time of t RAS reaches idle state to begin normal operation. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. with clock cycle RFC M52S128168A before the SDRAM RFC Publication Date: Dec. 2008 Revision: 1.2 13/47 ...
Page 14
... The DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA1 and BA0 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM’s RAS falling. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 14/47 ...
Page 15
... Read command ( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 15/47 ...
Page 16
... Before executing self refresh, all banks must be precharged. Burst stop command ( Low, RAS , CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 16/47 ...
Page 17
... ESMT No operation ( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 17/47 ...
Page 18
... M52S128168A ...
Page 19
... M52S128168A ...
Page 20
... D Q Elite Semiconductor Memory Technology Inc M52S128168A D 3 Publication Date: Dec. 2008 Revision: 1.2 20/47 ...
Page 21
... M52S128168A Publication Date: Dec. 2008 Revision: 1.2 21/47 ...
Page 22
... M52S128168A ...
Page 23
... determinates the last data write. RDL min delay) with DQM. RAS M52S128168A * ...
Page 24
... from self refresh exit command, any other command can not be accepted. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 24/47 ...
Page 25
... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 25/47 ...
Page 26
... NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M52S128168A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Row Active) Row Active) Row Active) Row Active) Publication Date: Dec. 2008 Revision: 1.2 Note 2 2 ...
Page 27
... ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M52S128168A ACTION Idle after tRP Idle after tRP Idle after tRP Row Active after tRCD Row Active after tRCD Idle after tRFC Idle after tRFC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: Dec ...
Page 28
... X X Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M52S128168A ACTION Note Idle after tRFC (ABI) 6 Idle after tRFC (ABI) 6 ABI 7 ABI Publication Date: Dec ...
Page 29
... ESMT Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3,Burst Length = 1 Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 29/47 ...
Page 30
... Enable auto precharge , precharge bank B at end of burst. 0 Enable auto precharge , precharge bank C at end of burst. 1 Enable auto precharge , precharge bank D at end of burst. Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M52S128168A Publication Date: Dec. 2008 Revision: 1.2 30/47 ...
Page 31
... Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS.. Elite Semiconductor Memory Technology Inc M52S128168A ...
Page 32
... Precharge Row Active ( A - Bank ) ( A - Bank ) SHZ M52S128168A ...
Page 33
... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. before row precharge , will be written. RDL Publication Date: Dec. 2008 Revision: 1.2 M52S128168A 33/47 ...
Page 34
... Note can be don’t cared when RAS , CAS and WE are high at the clock high going edge interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 ...
Page 35
... To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data interrupt burst write by Row precharge , both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 ...
Page 36
... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note : 1. t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 36/47 ...
Page 37
... ESMT Read & Write cycle with Auto Precharge @ Burst Length = 4 *Note : 1. t should be controlled to meet minimum t CDL (In the case of Burst Length = 1 & 2) Elite Semiconductor Memory Technology Inc. before internal precharge start. RAS M52S128168A Publication Date: Dec. 2008 Revision: 1.2 37/47 ...
Page 38
... ESMT Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4 *Note : 1. DQM is needed to prevent bus contention Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 38/47 ...
Page 39
... Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycles”. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 39/47 ...
Page 40
... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Dec. 2008 Revision: 1.2 40/47 ...
Page 41
... Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + t 3. Can not violate minimum refresh specification. (64ms) Elite Semiconductor Memory Technology Inc. prior to Row active command. SS M52S128168A Publication Date: Dec. 2008 Revision: 1.2 41/47 ...
Page 42
... CKE going high to complete self refresh exit. RFC 7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Elite Semiconductor Memory Technology Inc. M52S128168A is required before exit from self refresh. RAS Publication Date: Dec. 2008 Revision: 1 ...
Page 43
... Extended Mode Register Set Cycle M52S128168A ...
Page 44
... D 22.22 BSC E 11.76 BSC 10.16 BSC L 0.40 0.50 0.60 0.016 0.020 0.024 0.80 REF e 0.80 BSC Θ 0° 10° M52S128168A SEE DETAIL 0.21 REF 0.665 REF A 1 -C- DETAIL "A" SECTION B-B Dimension in inch Min Norm Max 0.047 0.018 0.008 ...
Page 45
... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Dimension in inch Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 7.90 8.00 8.10 0.311 7.90 8.00 8.10 0.311 6.40 6.40 0.80 M52S128168A Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.315 0.319 0.315 0.319 0.252 0.252 0.031 Publication Date: Dec. 2008 Revision: 1.2 45/47 ...
Page 46
... ESMT Revision History Revision 1.0 1.1 1.2 Elite Semiconductor Memory Technology Inc. Date 2007.05.29 Original 1. Add Speed -7 spec. 2007.10.08 2. Modify Icc spec 1. Move Revision History to the last 2008.12.09 2. Modify the description about self refresh operation M52S128168A Description Publication Date: Dec. 2008 Revision: 1.2 46/47 ...
Page 47
... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52S128168A Publication Date: Dec. 2008 Revision: 1.2 47/47 ...