m52s64164a Elite Semiconductor Memory Technology Inc., m52s64164a Datasheet
m52s64164a
Manufacturer Part Number
m52s64164a
Description
1m X 16 Bit X 4 Banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
1.M52S64164A.pdf
(47 pages)
ESMT
SDRAM
FEATURES
GENERAL DESCRIPTION
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT (Top View)
Elite Semiconductor Memory Technology Inc.
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
- PASR (Partial Array Self Refresh)
- TCSR (Temperature Compensated Self Refresh)
- DS (Driver Strength)
2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
Special function support
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
The M52S64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
A
LDQM
10
V
V
V
V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS
RAS
BA0
BA1
V
DDQ
V
V
DDQ
SSQ
SSQ
WE
/AP
CS
DD
DD
A
A
A
A
DD
0
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DQ15
V
DQ14
DQ13
V
DQ12
DQ11
V
DQ10
DQ9
V
DQ8
V
NC
UDQM
CLK
CKE
NC
A
A
A
A
A
A
A
V
SS
SSQ
DDQ
SSQ
DDQ
SS
11
9
8
7
6
5
4
SS
A
B
C
D
E
F
G
H
J
UDQM
DQ12
VSS
DQ14
DQ10
DQ8
VSS
NC
A8
1
ORDERING INFORMATION
M52S64164A-7.5TG
M52S64164A-10TG
M52S64164A-7.5BG
M52S64164A-10BG
DQ15
DQ13
DQ11
DQ9
CLK
NC
A11
A5
A7
2
PRODUCT ID
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
3
A4
4
1M x 16 Bit x 4 Banks
5
Synchronous DRAM
6
133MHz 54 Pin TSOP II
100MHz 54 Pin TSOP II
133MHz
100MHz
Publication Date: Sep. 2008
FREQ.
Revision: 1.4
MAX
VDDQ
VSSQ
VSSQ
VDDQ
VDD
CAS
BA0
7
A0
A3
M52S64164A
LDQM
DQ0
DQ2
DQ4
DQ6
BA1
RAS
A1
A2
8
54 Ball BGA
54 Ball BGA
PACKAGE
VDD
DQ1
DQ3
DQ7
DQ5
VDD
A10
WE
CS
9
Comments
1/47
Pb-free
Pb-free
Pb-free
Pb-free
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