hn58x2502fpiag Renesas Electronics Corporation., hn58x2502fpiag Datasheet
hn58x2502fpiag
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hn58x2502fpiag Summary of contents
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HN58X2502IAG HN58X2504IAG Serial Peripheral Interface 2k EEPROM (256-word × 8-bit) 4k EEPROM (512-word × 8-bit) Electrically Erasable and Programmable Read Only Memory Description HN58X25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and Programmable ROM). It realizes ...
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... HN58X2502IAG/HN58X2504IAG Ordering Information Type No. Internal organization Operating voltage 2-kbit (256 × 8-bit) HN58X2502FPIAG 4-kbit (512 × 8-bit) HN58X2504FPIAG 2-kbit (256 × 8-bit) HN58X2502TIAG 4-kbit (512 × 8-bit) HN58X2504TIAG Pin Arrangement V Pin Description Pin name C Serial clock D Serial data input Q Serial data output ...
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HN58X2502IAG/HN58X2504IAG Block Diagram HOLD D Q Absolute Maximum Ratings Parameter Supply voltage relative Input voltage relative Operating temperature range* Storage temperature range Notes: 1. Including electrical ...
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HN58X2502IAG/HN58X2504IAG DC Characteristics Parameter Input leakage current Output leakage current V current Standby CC Active Output voltage Rev.1.00, Nov.16.2006, page Symbol Min Max I ...
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HN58X2502IAG/HN58X2504IAG AC Characteristics Test Conditions • Input pules levels: V × 0 V × 0 • Input rise and fall time: ≤ • Input and output timing reference ...
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HN58X2502IAG/HN58X2504IAG Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time Clock high time Clock low time Clock rise time Clock fall time Data in setup ...
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HN58X2502IAG/HN58X2504IAG Timing Waveforms Serial Input Timing S t CHSL C t DVCH D High Impedance Q Hold Timing HOLD Output Timing S C ADDR D LSB IN t CLQV t CLQX Q Rev.1.00, Nov.16.2006, page 7 ...
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HN58X2502IAG/HN58X2504IAG Pin Function Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (C). Serial data input (D) This input signal is ...
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HN58X2502IAG/HN58X2504IAG Functional Description Status Register The following figure shows the Status Register Format. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. Status Register Format b7 1 ...
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HN58X2502IAG/HN58X2504IAG Write Enable (WREN): The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in the ...
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HN58X2502IAG/HN58X2504IAG Write Disable (WRDI): One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in the following figure, to send this instruction to the device, chip select (S) ...
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HN58X2502IAG/HN58X2504IAG Read Status Register (RDSR): The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When ...
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HN58X2502IAG/HN58X2504IAG Write Status Register (WRSR): The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...
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HN58X2502IAG/HN58X2504IAG Read from Memory Array (READ): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and the address bytes are then shifted in, ...
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HN58X2502IAG/HN58X2504IAG Write to Memory Array (WRITE): As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte ...
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HN58X2502IAG/HN58X2504IAG Byte Write (WRITE) Sequence (Page ...
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HN58X2502IAG/HN58X2504IAG Data Protect The Block Protect bits (BP1, BP0) define the area of memory that is protected against the execution of write cycle, as summarized in the following table. When Write Protect (W) is driven low, write to memory array ...
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HN58X2502IAG/HN58X2504IAG Notes Data Protection at V On/Off CC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger and turn When V CC the EEPROM to unintentional program mode. To ...
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... HN58X2502IAG/HN58X2504IAG Package Dimensions HN58X2502FPIAG/HN58X2504FPIAG (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code RENESAS Code P-SOP8-3.9x4.89-1.27 PRSP0008DF Index mark Rev.1.00, Nov.16.2006, page Previous Code MASS[Typ.] FP-8DBV 0.08g F 5 Terminal cross section ( Ni/Pd/Au plating ) NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" ...
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HN58X2502IAG/HN58X2504IAG HN58X2502TIAG/HN58X2504TIAG (PTSP0008JC-B / Previous Code: TTP-8DAV) JEITA Package Code RENESAS Code P-TSSOP8-4.4x3-0.65 PTSP0008JC Index mark Rev.1.00, Nov.16.2006, page Previous Code MASS[Typ.] TTP-8DAV 0.034g ...
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Revision History Rev. Date Page 1.00 Nov. 16, 2006 Initial issue HN58X2502IAG/HN58X2504IAG Data Sheet Contents of Modification Description ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...