sip11203 Vishay, sip11203 Datasheet
sip11203
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sip11203 Summary of contents
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... Both ICs also allow control of the discharge rate of the synchronous rectifier driver outputs during power-down. The SiP11203 and SiP11204 are available in a Pb-free MLP44-16 package and are rated to handle the industrial ambient temperature range °C. TYPICAL APPLICATION CIRCUIT ...
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... SiP11203/SiP11204 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Linear Inputs REF Storage Temperature Junction Temperature Package Thermal Impedance (Rθ Notes: a. Device mounted with all leads soldered to printed circuit board. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied ...
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... IN A and IN B low to OUT A/OUT B low t PDDET kΩ (Note forcing voltage bypassed by 1 µF to GND, INA or INB = 5 V, other I HOFF input = 0 V, force active output ( SiP11203/SiP11204 Vishay Siliconix Limits a b Min Typ 4.0 2.5 2.1 3.0 3.8 100 = 0 3 ...
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... step and vice versa REF. PIN CONFIGURATION OUTB R INB PGND 3 INA 4 OUTA GND R ORDERING INFORMATION Part Number SiP11203DLP-T1-E3 SiP11204DLP-T1-E3 www.vishay.com 4 Test Conditions Unless Otherwise Specified 5.5 V ≤ V ≤ °C A UVLO V Rising until output transitions ...
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... Input pin for over voltage detection 1.225 V reference voltage for converter output voltage regulating setting Capacitor value sets power down detection time in conjunction with R Resistor value sets currents for power down detection timer and for power down discharge of outputs Driver output B Figure 1. SiP11203/SiP11204 Vishay Siliconix PD www.vishay.com 5 ...
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... SiP11203/SiP11204 Vishay Siliconix DETAILED OPERATION SUPPLY VOLTAGE ( The SiP11203/SiP11204 are designed to operate at an input voltage (V ) between 5.5 V and 13 V. The syn- IN chronous rectifier drivers (OUTA and OUTB) are pow- ered directly from facilitate setting the gate drive IN voltage for the rectifier MOSFETs. Due to the high ...
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... Applications Information section. Output Over-voltage Protection: SiP11203 versus SiP11204 For maximum flexibility in the way that the SiP11203/ SiP11204 parts react to an output over-voltage event, the input to the over-voltage protect comparator (OVP ) is brought out separately from the error ampli- IN fier inputs ...
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... SRH SRL GND SRH SRL GND supply for SiP11203/SiP11204 is generated using the pulse transformer providing the IN synchronous rectifier timing signals • INA goes low, which would normally command the is OUTA driver to go low. This would prevent spurious L turn-on of the associated synchronous rectifier ...
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... IN both OUTA and OUTB being pulled low by their associated inverter MOSFETs. FUNCTIONAL BLOCK DIAGRAM Figure 3. During converter startup, the synchronous MOSFET gate-driver outputs of the SiP11203/SiP11204 are reversed and inverted START-UP DRIVER OPERATION Assuming that V rises with suitable rapidity to a volt- IN age greater than 5 ...
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... V Internal logic circuits enabled Figure 4. Soft-start parameters of the SiP11203/SiP11204 are programmable with external components NORMAL DRIVER OPERATION In normal operation, OUTA responds to INA, and OUTB to INB. The signal path from input to output is non-inverting. The output drivers have high and delib- erately asymmetrical current sink and source capabili- ties ( ...
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... This programma- SYNCHRONOUS RECTIFIER PHASE-IN AND RISING EDGE DELAY , OUT The SiP11203/SiP11204 has the ability to “phase in” the synchronous rectifiers at start-up. This causes the rectifier MOSFETs to initially be used as conventional PN (or Schottky) diodes, then as synchronous rectifi- ers for an increasing percentage of each switching cy- cle, until finally they are operating completely as synchronous switches ...
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... OUT B Phase-In period Figure 7. The SiP11203/SiP11204 gate-drive output signals are delayed during phase-in prevent disturbing the output voltage The Figure 8 below shows how the rising edge delay is implemented in conjunction with the Si9122 and allows the effective BBM2 and BBM4 falling delays to be www ...
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... BBM1 Figure 8. The delay of SiP11203 and SiP11204 gate-drive output signals compensate the break-before-make switching action OUTPUT OVER-VOLTAGE PROTECTION The SiP11203/SiP11204 provide output over-voltage protection (OVP) by means of a dedicated internal comparator. One input of the OVP comparator is brought out to the OVP pin, and the other is returned ...
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... SiP11203/SiP11204 Vishay Siliconix TYPICAL CHARACTERISTICS 1.28 1.26 1.24 1.22 1.2 1.18 1. Temperature (°C) V vs. Temperature REF 4 3.5 3 2.5 2 1 (mA) Error Amp MHz (V) Supply Current Without Load vs. V www.vishay.com 14 5.25 5.15 5.05 VIN = 7.5 V 4.95 4.85 4.75 100 150 0.8 0.7 0.6 0.5 0.4 0.3 0 500 kHz ...
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... DEL 300 250 200 150 100 1.6 1.5 1.4 1 1.2 1.1 1 100 150 SiP11203/SiP11204 Vishay Siliconix 7.5 V 1.5 ns/ kΩ DEL (kΩ) Rise Delay vs. R DEL (kΩ) Powerdown Timeout 100 Temperature (° ...
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... Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right ...