uc1697v ETC-unknow, uc1697v Datasheet
uc1697v
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uc1697v Summary of contents
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H IGH 128 x 128RGB C-STN LCD Controller-Driver w/ 16-bit per RGB On-Chip SRAM ES Specifications Revision 0 OLTAGE IXED IGNAL U Specifications and information herein are subject to change without notice. IC February 7, 2007 C ...
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... DISPLAY DATA RAM .................................................................................................... 44 RESET & POWER MANAGEMENT............................................................................... 47 MULTI-TIME PROGRAM NV MEMORY ........................................................................ 49 MTP OPERATION FOR LCM MAKERS ........................................................................ 50 ESD CONSIDERATION.................................................................................................. 55 ABSOLUTE MAXIMUM RATINGS................................................................................. 56 SPECIFICATIONS .......................................................................................................... 57 AC CHARACTERISTICS................................................................................................ 58 PHYSICAL DIMENSIONS .............................................................................................. 65 ALIGNMENT MARK INFORMATION............................................................................. 66 PAD COORDINATES ..................................................................................................... 67 TRAY INFORMATION .................................................................................................... 72 REVISION HISTORY ...................................................................................................... 73 Revision A_0 ABLE OF ONTENT UC1697v 128x128RGB CSTN Controller-Driver - 1 - ...
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... LRM (Line Rate Modulation) gray-shade modulation scheme to achieve well balanced shading, vivid colors, and natural-looking images. With UC1697v, LCD makers can now achieve TFT-like image quality, while maintaining the same STN advantages in power consumption, unit cost, ease of customization and production flexibility ...
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... RDERING NFORMATION OLD UMPED IE Part Number MTP UC1697vGAA Yes General Notes A I PPLICATION NFORMATION For improved readability, the specification contains many application data points. When application information is given advisory and does not form part of the specification for the device. B ...
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... IAGRAM POWER ON & RESET CONTROL CLOCK & TIMING GENERATOR CONTROL & STATUS REGISTER DISPLAY DATA LATCHES COMMAND HOST INTERFACE Revision A_0.6 128x128RGB CSTN Controller-Driver COLUMN ADDRESS GENERATOR DISPLAY DATA RAM LEVEL SHIFTERS V LCD GENERATOR SEG DRIVERS UC1697v C & BIAS L 3 ...
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U C LTRA HIP High-Voltage Mixed-Signal ESCRIPTION Name Type # of Pads PWR 9 DD2 V 2 DD3 GND V 12 SS2 LCD ...
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... Host Interface for more detail. In parallel mode, the meaning of WR[1:0] depends on whether the interface is in the 6800 mode or the 8080 mode. In serial interface modes, these two pins are not used, connect them to V UC1697v 128x128RGB CSTN Controller-Driver Mode 6800/16-bit 8080/16-bit ...
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U C LTRA HIP High-Voltage Mixed-Signal IC Name Type # of Pads D0~D15 I Description D B ATA US Bi-directional bus for parallel host interfaces. In serial modes, connect DB[0] to SCK, DB[8] to SDA. BM=1x BM=0x BM=0x ...
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... TST4 is also used as one of the high voltage power supply for MTP programming operation. For COG designs, please wire out TST4 with trace resistance between 30~50 :. Test I/O pins. Leave these pins open during normal use. UC1697v 128x128RGB CSTN Controller-Driver bus within DD power to the chip externally ...
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... With its high DD speed data-write condition, UC1697v’s peak current (I write to UC1697v’s on-chip SRAM. Such high pulsing current mandates very careful design of V trances in COG glass modules. When V current can cause the actual on-chip V ...
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... ONTROL EGISTERS UC1697v contains registers which control the chip operation. The following table is a summary of these control registers, a brief description and the default values. These registers can be modified by commands, which will be described in the next two sections, starting with a summary table, followed by a detailed instruction-by-instruction description ...
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U C LTRA HIP High-Voltage Mixed-Signal IC Name Bits Default DC 5 18H Display Control: DC[0] : PXV: Pixels Inverse. Bit-wise data inversion. (Default 0: OFF) DC[1] : APO: All Pixels ON (Default 0: OFF) DC[2] : Display ON/OFF (Default ...
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... ID 2 PIN Access the connected status of ID pins. Revision A_0.6 128x128RGB CSTN Controller-Driver Description 000 : Idle 001 : Read 010 : Erase 011 : Program 1xx : For UltraChip’s debug use only 1: Use fine tune. LCD Status Registers 01b: (Not used) 11b: Normal UC1697v 11 ...
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... U C LTRA HIP High-Voltage Mixed-Signal OMMAND ABLE The following is a list of host commands supported by UC1697v C/D: 0: Control, W/R: 0: Write Cycle, #: Useful Data bits Command C/D W/R 1 Write Data Byte Read Data Byte Get Status & Set Column Address LSB Set Column Address MSB ...
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... D[7:0] = 0010 1011 D[7:0] = 1000 0001 D[7:0] = 1000 1011 0010 1011 1000 0001 1000 1011 UC1697v 128x128RGB CSTN Controller-Driver D0 Action Default 0 0 Set N MTP1 Shared with 0 1 Set N/A Window # # MTP2 Program 1 0 Set N/A commands # # MTP3 1 1 Set ...
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... ESCRIPTION ( RITE ATA O ISPLAY EMORY Action Write data UC1697v will convert input RAM data to 16-bit of RGB data. Please refer to command Set Color Mode for detail of data-write sequence. ( EAD ATA ROM ISPLAY EMORY Action Read data Each RGB triplet is stored as 16-bit in the display RAM. Each 16-bit of RGB data takes RAM read cycles for – ...
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... C/D W (x10) LCD C/D W APC register parameter UC1697v CA6 CA5 CA4 TC1 TC0 o 11b = -0.05 PC1 PC0 PC3 PC2 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC ( CROLL INE Action Set Scroll Line LSB SL[3:0] Set Scroll Line MSB SL[6:4] Set the number of lines for scroll area. Scroll line setting will scroll the displayed ...
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... Command Description (34) ~ (37) for more details. If WPC[1:0] and WPP[1:0] values are the default values, the behavior of CA, RA auto-increment will be the same, no matter what the setting of AC[3] is. Revision A_0.6 128x128RGB CSTN Controller-Driver C/D W C/D W UC1697v LC9 LC8 AC2 AC1 AC0 17 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC (14 IXED INES Action Set Fixed Lines {FLT, FLB} (Double-byte command) The fixed line function is used to implement the partial scroll function by dividing the screen into scroll ...
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... When DC[2] is set to 0, the IC will put itself into Sleep mode. All drivers, voltage generation circuit and timing circuit will be halted to conserve power. When DC[2] is set to 1, UC1697v will first exit from Sleep mode, restore the power and then turn on COM drivers and SEG drivers. There is no other explicit user action or timing sequence required to enter or exit the Sleep mode ...
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... Default : 17 lines ) NIV[6]: 0b: non-XOR 13 NIV[6]= NIV[6]=1 13 (21 OLOR ATTERN Action Set Color Pattern LC [5] UC1697v supports on-chip swapping of R LC[5] SEG1 SEG2 SEG3 The definition of R/G/B input data is determined by LC[7:6], as described in Set Color Mode below. 20 C/D W ...
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... D[15: D[7: D[15: UC1697v LC7 LC6 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC Green Enhance Mode enabled (DC[4]=0): LC[7:6] = 00b ( RRR-GGG-BB, 256-color ) 8 bits of input RGB data are stored to 16 RAM bits. No dither is performed. Data Write Sequence (8-bit) st ...
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... 010b = 11 011b = 12 C/D W CEN register parameter C/D W DST register parameter UC1697v BR2 BR1 BR0 ...
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... RAM to each COM electrodes. The image displayed by each pixel row is therefore not affected by the setting of these three registers. When LC[9]=1, two partial display modes are possible with UC1697v: LC[8]=1: ON-OFF only, ultra-low-power mode (if Mux-Rate U 33, set BR=6). LC[8]=0: Full gray shade low power mode (BR and PM stays the same) When LC[9:8]=10b, the Mux-Rate is still CEN+1 ...
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... OLUMN DDRESS C/D W WPC1 register parameter A OW DDRESS C/D W WPP1 register parameter UC1697v 128x128RGB CSTN Controller-Driver ...
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... AC[3]=1: Outside Mode When Window Programming is under “Outside” mode, the CA and RA increment and wrap-around boundary will cover the entire UC1697v SRAM map (CA: 0~127, RA:0~127). However, when CA/RA points to a memory location within the window defined by registers WPC0, WPC1, WPP0, and WPP1, the SRAM data update operation will be suspended, the existing data will be retained and the input data will be ignored ...
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... Normal Y-mirror X-mirror X-mirror Y-mirror X-Y Exchange X-Y Exchange Y-mirror X-Y Exchange X-mirror X-Y Exchange X-mirror Y-mirror Revision A_0.6 128x128RGB CSTN Controller-Driver Image in the Host (MPU) Image in Display Data Ram (Start : (Physical origin: upper left corner) UC1697v 27 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC (36) S MTP PERATION ONTROL Action Set MTPC [4:0] (Double-byte command) This command is for MTP operation control: MTPC[2:0] : MTP command 000 : Sleep 010 : MTP Erase 1xx ...
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... PM setting (use with BR=001) and is only valid when MTPC[3]=1. C/D W Shared register parameter C/D W Shared register parameter UC1697v 128x128RGB CSTN Controller-Driver ...
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... DST, DEN, FLT, FLB, and partial display control flags LC[9:8] and LC[0]. Combined with low power partial display mode and a low bias ratio of 6, UC1697v can support wide variety of display control options. For example, when a system goes into stand-by mode, a large portion of LCD screen can be turned off to conserve power ...
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... For good product reliability, please keep V 2. The integer values of BR above are for reference only and may have slight shift. Revision A_0 (mV) PM_reg PM 0 13.14 255 0 21.90 255 0 24.09 198 0 26.28 141 0 19.71 255 o V -PM-BR relationship LCD under 16.5V over all temperature. LCD UC1697v 128x128RGB CSTN Controller-Driver V (V) LCD 6.40 9.75 10.67 16.25 11.74 16.51 12.80 16.51 9.60 14.63 31 ...
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U C LTRA HIP High-Voltage Mixed-Signal ENERATOR EFERENCE IRCUIT VDD VDD VDD2/VDD3 VDD2 VDD3 VSS VSS2 F 1: Sample circuit using internal Hi-V generator circuit IGURE N : OTE Sample component values: ...
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... DC[2] is set to OFF (logic “0”), both COM and SEG drivers will become idle and UC1697v will put itself into Sleep mode to conserve power. When DC[2] is set to ON, the DE flag will become “1”, and UC1697v will first exit from Sleep mode, restore the power ( etc.) and then turn on ...
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... High-Voltage Mixed-Signal NPUT OLOR ORMATS UC1697v supports the following two different input color formats. 256C (8-bit/RGB): In this color mode, R/G/B will be extended and the input data will be converted into 3R-3G-2B format before they are stored to display RAM. 4KC (12-bit/RGB): In this color mode, R/G/B will ...
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... ITO AYOUT AND ELECTION Since COM scanning pulses of UC1697v can be as short as 15PS critical to control the RC delay of COM and SEG signal to minimize crosstalk and maintain good mass production consistency. COM T RACES Excessive COM scanning pulse RC decay can cause fluctuation of contrast and increase COM direction crosstalk ...
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U C LTRA HIP High-Voltage Mixed-Signal IC RAM W/R POL COM1 COM2 COM3 SEG1 SEG2 F IGURE 36 2: COM and SEG Driving Waveform ©1999 ~ 2007 ES Specifications ...
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... H I OST NTERFACE As summarized in the table below, UC1697v supports two parallel bus protocols, in either 8-bit or 16-bit bus width, and three serial bus protocols. Designers can either use parallel buses to achieve high data transfer rate, or use serial buses to create compact LCD modules. ...
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... I ARALLEL NTERFACE The timing relationship between UC1697v internal control signal RD, WR and their associated bus actions are shown in the figure below. The Display RAM read interface is implemented as a two-stage pipe-line. This architecture requires that, every time memory address is modified, either in 8-bit mode or 16-bit mode, by either Set CA, or Set RA command, a dummy read cycle needs to be performed before the actual data can propagate through the pipe-line and be read from data port D ...
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... S I ERIAL NTERFACE UC1697v supports three serial modes, a 4-wire SPI mode (S8), a compact 3/4-wire mode (S8uc), and a 3- wire mode (S9). Bus interface mode is determined by the wiring of the BM[1:0], DB[15] and DB[13]. See table on last page for more detail WIRE NTERFACE Only write operations are supported in 4-wire serial mode ...
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... VDD ID1 BM1 BM0 5: 8080/16-bit parallel mode example VDD DB15 DB13 DB7 ~ DB0 CD WR0(WR) WR1(RD) CS0 DECODER CS1 VDD RST ID0 ID1 BM1 BM0 6: 8080/8-bit parallel mode example ©1999 ~ 2007 VDD VDD UC1697v VSS VDD VDD UC1697v VSS ES Specifications ...
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... RST ID0 VDD ID1 BM1 BM0 7: 6800/16-bit parallel mode example VDD DB15 DB13 DB7 ~ DB0 CD WR0(R/W) WR1(E) CS0 DECODER CS1 VDD RST ID0 ID1 BM1 BM0 8: 6800/8-bit parallel mode example UC1697v VDD VDD UC1697v VSS VDD VDD UC1697v VSS 41 ...
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... WR1 CS0 DECODER CS1 VDD RST ID0 ID1 BM1 BM0 9: 4-Wires SPI (S8) serial mode example VDD DB15 DB13 SCK(DB0) SDA(DB8) CD WR0 WR1 CS0 VDD RST ID0 ID1 CS1 BM1 BM0 ©1999 ~ 2007 VDD VDD UC1697v VSS VDD VDD UC1697v VSS ES Specifications ...
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... VCC SCK SDA ADDRESS MPU IORQ GND F 11: 3/4-Wires SPI (S9) serial mode example IGURE Revision A_0.6 128x128RGB CSTN Controller-Driver VDD VDD DB15 VDD DB13 SCK(DB0) SDA(DB8) CD WR0 WR1 CS0 UC1697v DECODER CS1 VDD RST ID0 ID1 VDD BM1 BM0 VSS UC1697v 43 ...
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U C LTRA HIP High-Voltage Mixed-Signal RAM ISPLAY ATA D O ATA RGANIZATION The input display data (depend on color mode) are stored to a dual port static RAM (RAM, for Display Data RAM) organized as 128x128x16. ...
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... Specify the starting point of data-write by issuing commands Set Window Program Starting Column Address, and Set Window Program Starting Row Address. Example 2 (AC[2:0] = 111) : AC[ (127, 0) (WPP0, WPC0) (WPP1,WPC1) Example 2-1 : AC[ (127, 0) (WPP0, WPC0) (WPP1,WPC1) UC1697v 128x128RGB CSTN Controller-Driver to or from ( WPC0 WPC1 MC ...
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U C LTRA HIP High-Voltage Mixed-Signal IC Row Adderss 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 68H 69H ...
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... V and V are ready before releasing COM LCD BIAS and SEG drivers from their idle states. When exiting Sleep or Reset mode, COM and SEG drivers will not be activated until UC1697v internal voltage sources are restored to their proper values. UC1697v M ODE Mode OM Reset ...
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... High-Voltage Mixed-Signal OWER P EQUENCE UC1697v power-up sequence is simplified by built- in “Power Ready” flags and the automatic invocation of System-Reset command after Power- ON-Reset. System programmers are only required to wait 150 mS before the CPU starting to issue commands to UC1697v. No additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to RAM or any other commands ...
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... S U PERATION FOR THE YSTEM SERS For the MTP version of UC1697v, the content of the NV memory will be read automatically after the power-on and hardware pin RESET. There is no user intervention or external power source required. When set up properly, the V fine tuned to achieve high level of consistency for the LCM contrast ...
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U C LTRA HIP High-Voltage Mixed-Signal IC MTP O LCM M PERATION FOR 1. High voltage supply and timer setting In MTP Program operation, two different high voltages are needed. In chip design, one high voltage is generated by internal ...
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... There are 6 MTP cell bits. They are divided into two groups for different purpose. MTP[5: Trim LCD When PMO[5]=1: PM with trim = PM - PMO[4:0] When PMO[5]=0: PM with trim = PM + PMO[4:0] Revision A_0.6 128x128RGB CSTN Controller-Driver Program Program/Erase V =12V Read to verify LCD V =6.4V LCD may repeat 3 times Waveform LCD UC1697v 51 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC MTP OMMAND EQUENCE AMPLE The following tables are examples of command sequence for MTP Program and Erase operations. These are only to demonstrate some “typical, generic” scenarios. Designers are ...
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... Set MTP Write Mask MTPM1 Set MTP Control =0V DD UC1697v 128x128RGB CSTN Controller-Driver Comments Set LC[4:3]=11b Set MTP V LCD MTP2: 00h(6.4V) Set MTP V LCD MTP3: 3Dh(12V) Set MTP Timer MTP4: 50h(100mS) Set MTP Timer MTP5: 08h(10mS) ...
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U C LTRA HIP High-Voltage Mixed-Signal AMPLE OWER ANAGEMENT OMMAND The following tables are examples of command sequence for power-up, power-down and display ON/OFF operations. These are only to demonstrate some “typical, generic” scenarios. Designers ...
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... ESD damage during handling and manufacturing process therefore highly recommended that LCM makers strictly follow the "JESD 625-A Requirements for Handling Electrostatic- Discharge-Sensitive (ESDS) Devices" when manufacturing LCM. The following pins in UC1697v require special "ESD Sensitivity" consideration in particular: Test Mode LCD Driver ...
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U C LTRA HIP High-Voltage Mixed-Signal BSOLUTE AXIMUM ATINGS In accordance with IEC134, Note 1 and 2 Symbol V Logic Supply voltage DD V LCD Generator Supply voltage DD2 V Analog Circuit Supply voltage DD3 V ...
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... Temp = 16.5V LCD V = 16.5V LCD = 16.5V LCD O LC[4:3] = 10b 92, Panel Loading (PC[1:0 MTP All HV outputs are open circuit. Conditions Bus = idle Bus = idle Reset (stand-by current) UC1697v 128x128RGB CSTN Controller-Driver Min. Typ. Max. Unit 1.65 3.3 V 2.5 3.3 V 15.2 16.5 V 0.93 1. ...
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U C LTRA HIP High-Voltage Mixed-Signal HARACTERISTICS CD t AS80 CS0 CS1 t CSSA80 t PWR80 WR0 WR1 Write D[7:0] t ACC80 Read D[7:0] F 15: Parallel Bus Timing Characteristics (for 8080 MCU) IGURE (2. ...
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... Description Condition 16-bit bus (read) (write) 8-bit bus (read) (write) 8-bit (read) 8-bit (write) 16-bit bus (read) (write) 8-bits bus (read) (write 100pF L UC1697v 128x128RGB CSTN Controller-Driver Min. Max. Units 0 – – nS 320 270 180 145 160 – 135 – ...
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U C LTRA HIP High-Voltage Mixed-Signal AS68 CS0 CS1 t CSSA68 t PWR68 WR1 Write D[7:0] t ACC68 Read D[7:0] F 16: Parallel Bus Timing Characteristics (for 6800 MCU) IGURE (2. 3.3V, Ta= –30 ...
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... C) Description Condition 16-bit bus (read) (write) 8-bit bus (read) (write) 8-bit (read) 8-bit (write) 16-bit bus (read) (write) 8-bit bus (read) (write 100pF L UC1697v 128x128RGB CSTN Controller-Driver Min. Max. Units 0 – – nS 320 270 180 145 160 – 135 – ...
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U C LTRA HIP High-Voltage Mixed-Signal ASS8 CS0 CS1 t CSSAS8 t LPWS8 SCK t DSS8 SDA 17: Serial Bus Timing Characteristics (for S8/S8uc) F IGURE (2. 3.3V, Ta= –30 to +85 DD Symbol ...
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... DSS9 t Data hold time DHS9 t CS1/CS0 CSSAS9 Chip select setup time t CSHS9 Revision A_0.6 t CYS9 t WHS9 t DHS9 C) Description Condition o C) Description Condition UC1697v 128x128RGB CSTN Controller-Driver t CSHS9 Min. Max. Units 40 – – – – Min. Max. ...
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U C LTRA HIP High-Voltage Mixed-Signal WR[1:0] (1.65V 3.3V, Ta= –30 to +85 DD Symbol Signal t RST Reset low pulse width RW t RST, WR Reset to WR pulse delay ...
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... UMP EIGHT within die MAX MIN UMP IZE 2 SEG /COM: 14.5x138 UMP ITCH 26 UMP GAP 12 OORDINATE RIGIN Chip center (Drawing and coordinates are for the Circuit/Bump view.) Revision A_0.6 UC1697v 128x128RGB CSTN Controller-Driver 65 ...
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U C LTRA HIP High-Voltage Mixed-Signal LIGNMENT ARK NFORMATION U-Left Mark D-Left Mark S : HAPE OF THE ALIGNMENT MARK OORDINATES 1 -5374.5 -5363.3 2 -5346.5 3 -5419.8 1 ...
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... VDD 45 119 121 VDD 45 119 122 VDD 45 119 123 VDD 45 119 124 VDD 45 119 125 DUMMY 45 119 126 DUMMY UC1697v 128x128RGB CSTN Controller-Driver -4121.9 -541.5 45 119 -3875.9 -541.5 45 119 -3815.9 -541.5 45 119 -3569.9 -541.5 45 119 -3509.9 -541.5 45 119 -3263 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC # Pad X Y 127 DUMMY 1639.525 -541.5 128 DUMMY 1699.525 -541.5 129 DUMMY 1759.525 -541.5 130 DUMMY 1819.525 -541.5 131 DUMMY 1879.525 -541.5 132 DUMMY 1939.525 -541.5 133 VDD2 2125.45 -541.5 134 ...
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... SEG152 14.5 138 381 SEG153 14.5 138 382 SEG154 14.5 138 383 SEG155 14.5 138 384 SEG156 14.5 138 385 SEG157 14.5 138 386 SEG158 UC1697v 128x128RGB CSTN Controller-Driver 2610.25 533 14.5 138 2583.75 533 14.5 138 2557.25 533 14.5 138 2530.75 533 14.5 138 2504.25 533 14.5 138 2477 ...
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U C LTRA HIP High-Voltage Mixed-Signal IC # Pad X Y 387 SEG159 887.75 533 388 SEG160 861.25 533 389 SEG161 834.75 533 390 SEG162 808.25 533 391 SEG163 781.75 533 392 SEG164 755.25 533 393 SEG165 728.75 533 394 ...
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... UC1697v 128x128RGB CSTN Controller-Driver -4279.75 533 14.5 138 -4306.25 533 14.5 138 -4332.75 533 14.5 138 -4359.25 533 14.5 138 -4385.75 533 14.5 138 -4412.25 533 14.5 138 -4438.75 533 14 ...
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U C LTRA HIP High-Voltage Mixed-Signal RAY NFORMATION 72 ©1999 ~ 2007 H20-58x453-22 ES Specifications ...
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... R H EVISION ISTORY Revision 0.6 Revision A_0.6 128x128RGB CSTN Controller-Driver Contents First Release UC1697v Date of Rev. Feb. 7, 2007 73 ...