ak4673 AKM Semiconductor, Inc., ak4673 Datasheet
ak4673
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ak4673 Summary of contents
Page 1
... Screen Controller (TSC) which includes the SAR type ADC. The AK4673 features analog mixing circuits, PLL and a 4-wire resistive touch screen I/F that allows easy interfacing in mobile phone and portable A/V player designs. The AK4673 is available in a 57pin BGA package, utilizing less board space than competitive offerings. ...
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... AVDD (Analog): 2.6 ∼ 3.6V • DVDD (Digital): 2.6 ∼ 3.6V • HVDD (Headphone): 2.6 ∼ 5.25V • TVDD1 (Digital I/O): 2.5 ∼ 3.6V • TVDD2 (Digital I/O): 1.6 ∼ 3.6V • TSVDD (Touch Screen Controller): 2.5 ∼ 3.6V 13. Package: 57pin BGA (5mm x 5mm, 0.5mm pitch) MS0670-E- DSP Mode - 2 - [AK4673 DSP Mode 2007/10 ...
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... PENIRQN TSVDD TVDD1 SCLT SDAT PEN INTERRUPT Control Register SAR A/D Stereo ALC Reduction Separation Audio I/F Stereo ALC HPF Separation PMPLL PLL VSS3 VCOM DVDD [AK4673] I2CA CADT CADA SCLA SDAA PDN TVDD2 BICK LRCK SDTO SDTI MCKO MCKI * VCOC 2007/10 ...
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... Ordering Guide AK4673EG AKD4673 Evaluation board for AK4673 ■ Pin Layout MUTET RIN4/IN4 ROUT/LON LIN4/IN4+ 6 LOUT/LOP MIN/LIN3 5 NC RIN2/IN2- 4 TSVDD LIN2/IN2+ 3 LIN1/IN1 VCOM RIN1/IN1 VSS1 A B MS0670-E-01 −30 ∼ +85°C 57pin BGA (0.5mm pitch) ...
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... No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Mute Time Constant Control Pin B9 MUTET O Connected to VSS2 pin with a capacitor for mute time constant. MS0670-E-01 PIN/FUNCTION Function 2 C bus Slave Address (CADA) bit Select Pin - 5 - [AK4673] Table 61. 2007/10 ...
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... No internal bonding. This pin should be connected to ground (VSS1, VSS2 or VSS3 pin). Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, RIN4, LIN4, XP, YP, XN and YN) should not be left floating. MS0670-E- bus Slave Address(CADT) bit Select Pin 2 C serial data serial clock [AK4673] 2007/10 ...
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... MPWR, VCOC/RIN3, HPR, HPL, MUTET, RIN4/IN4−, LIN4/IN4+, ROUT/LOP, Analog LOUT/LON, MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+, XP, YP, XN, YN, PENIRQN MCKO Digital MCKI MS0670-E-01 Setting These pins should be open. This pin should be open. This pin should be connected to VSS2 [AK4673] 2007/10 ...
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... The PDN pin should be set to “H” after all power supplies are powered-up. The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. ...
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... ADC → IVOL, IVOL=0dB, ALC=OFF - (Note 11) 0.168 (Note 12) 1. (Note 11) 76 (Note 12) - (Note 11) 76 (Note 12) - (Note 11) 75 (Note 12) - (Note 11) - (Note 12 [AK4673] typ max Units +20 - + 0.228 - 0.114 - 0.057 2.47 2. 0.198 0.228 1.98 2. dBFS 83 - dBFS 88 - dBFS 72 ...
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... L LOVL bit = “0” 1.78 LOVL bit = “1” 2. LODIF bit = “1”, R =10kΩ for each pin (Full-differential) L LOVL bit = “0” 3.52 LOVL bit = “1” [AK4673] typ max Units - 16 Bits 1.98 2.18 Vpp 2.50 2.75 Vpp 88 - dBFS 92 - 100 - 0.1 0 kΩ ...
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... C2 in Figure 2 - =22.8Ω. L =100Ω. L HPL/HPR pin 47μF C1 0.22μF 10Ω Figure 2. Headphone-Amp output circuit - 11 - typ max 1.98 2.38 3.00 3.60 1 0.1 0.8 0.1 0 300 Measurement Point 6.8Ω 16Ω C2 [AK4673] Units Vpp Vpp Vrms Vrms dBFS dBFS dBFS dBFS Ω 2007/10 ...
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... HPG bit = “0” HPG bit = “1” −10.5 LOVL bit = “0” LOVL bit = “1” - −4.5 LOVL bit = “0” LOVL bit = “1” - −10.5 HPG bit = “0” HPG bit = “1” [AK4673] typ max Units 1.98 - Vpp 0 +4 −20 −15.5 −16 ...
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... Note 24. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1”. Note 25. All digital input pins are fixed to each supply pin (TVDD1, TVDD2 or TSVDD) or (VSS2 or VSS3). MS0670-E-01 min 24) (Note 25 [AK4673] typ. max. Units 12 Bits 12 Bits ±2 LSB ±1 LSB ± ...
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... 4.4 1.8 0. 3.8 1 5.5 1.6 0. 3.5 1.5 0. 8.3 2.7 0.03 [AK4673 0.2 21.2 5 35.1 5 22.8 0.2 24.2 0.2 17.3 5 52.9 2007/10 ...
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... FR - −0.5dB - −0.1dB - ±0.1dB PB 0 −0.7dB - −6.0dB - SB 25 28) −3.0dB FR - −0.5dB - −0.1dB - [AK4673] typ max Units - 17.3 kHz 19.4 - kHz 19.9 - kHz 22.1 - kHz - - kHz ±0 1/fs μ 19.6 kHz 20.0 - kHz 22.05 ...
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... Duty tBCK tBCK dBCK - 16 - min Typ max - - - - - - - - - - 30%TVDD1 - - 30%TVDD2 - - 25%TVDD2 - - 30%TSVDD - - - - - - - - 0 0 0.4 ± typ max - 12.288 tBCK - - 1/(32fs 1/(64fs [AK4673] Units μA Units MHz ns ns MHz % % kHz 2007/10 ...
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... Duty 45 - tBCK 312.5 - tBCKL 130 - tBCKH 130 - - 17 - [AK4673] max Units 27 MHz - 12.288 MHz kHz 1/fs − tBCK 1/(32fs kHz 1/fs − tBCK 1/(32fs ...
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... S) −40 tMBLR 30) −70 tLRD −70 tBSD tSDH 50 tSDS 50 tLRB 50 31) tBLR 50 32) tLRD - tBSD - tSDH 50 tSDS [AK4673] typ max Units - 12.288 MHz - 13.312 MHz - 13.312 MHz - - kHz tBCK - 1/(32fs 1/(64fs ...
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... registered trademark of Philips Semiconductors. Note 34. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 35. The AK4673 can be reset by the PDN pin = “L”. Note 36. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. ...
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... Figure 3. Clock Timing (PLL/EXT Master mode) tLRCKH tDBF tBSD MSB tSDS tSDH - 20 - VIH2 VIL2 50%TVDD2 tLRCKL 100 50%TVDD2 tBCKL / tBCK x 100 50%TVDD2 50%TVDD2 50%TVDD2 50%TVDD2 50%TVDD2 VIH2 VIL2 [AK4673] 2007/10 ...
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... Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”) LRCK BICK SDTO SDTI Figure 6. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode) MS0670-E-01 tLRCKH tDBF tBSD tSDS tMBLR tLRD tSDS tSDH - 21 - [AK4673] 50%TVDD2 50%TVDD2 50%TVDD2 50%TVDD2 MSB tSDH VIH2 VIL2 50%TVDD2 50%TVDD2 tBSD 50%TVDD2 VIH2 VIL2 2007/10 ...
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... Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”) MS0670-E-01 1/fs tLRCKH tBCK tBCKH tBCKL 1/fs tLRCKH tBCK tBCKH tBCKL - 22 - [AK4673] VIH2 VIL2 tBLR VIH2 VIL2 VIH2 VIL2 VIH2 VIL2 tBLR VIH2 VIL2 VIH2 ...
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... Duty = tLRCKH 100 tBCK tBCKH tBCKL fMCK tMCKL dMCK = tMCKL x fMCK x 100 tLRCKH tLRB tBSD MSB tSDS MSB - 23 - VIH2 VIL2 VIH2 VIL2 tLRCKL 100 VIH2 VIL2 50%TVDD2 VIH2 VIL2 VIH2 VIL2 VIH2 VIL2 50%TVDD2 tSDH VIH2 VIL2 [AK4673] 2007/10 ...
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... MS0670-E-01 tLRCKH tLRB tBSD tSDS 1/fCLK tCLKH tCLKL 1/fs Duty = tLRCKH 100 tLRCKH tLRCKL tBCK tBCKH tBCKL Figure 12. Clock Timing (EXT Slave mode [AK4673] VIH2 VIL2 VIH2 VIL2 VIH2 VIL2 50%TVDD2 MSB tSDH VIH2 MSB VIL2 VIH2 VIL2 VIH2 VIL2 tLRCKL 100 ...
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... Figure 14 Bus Mode Timing (Audio) tHIGH tR tF tHD:DAT tSU:DAT tSU:STA 2 Figure 15 Bus Mode Timing (TSC VIH2 VIL2 VIH2 VIL2 50%TVDD2 VIH2 VIL2 tSP tSU:STO Start tSP tSU:STO Start [AK4673] VIH1 VIL1 VIH1 VIL1 Stop VIH3 VIL3 VIH3 VIL3 Stop 2007/10 ...
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... PMADL bit or PMADR bit SDTO PDN MS0670-E-01 tPDV Figure 16. Power Down & Reset Timing 1 tPD Figure 17. Power Down & Reset Timing [AK4673] 50%TVDD2 VIL1 2007/10 ...
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... AK4673 goes to master mode by changing M/S bit = “1”. When the AK4673 is used in master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4673 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state ...
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... When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time, when the AK4673 is supplied stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes is shown in ...
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... N/A BICK pin LRCK pin “L” Output “L” Output Invalid See Table 11 1fs Output MCKO pin MCKO bit = “1” Invalid Invalid Output [AK4673] (Table Invalid 2007/10 ...
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... Figure 18. PLL Master Mode PS1 bit PS0 bit BICK Output BCKO bit Frequency 0 32fs 1 64fs Table 11. BICK Output Frequency at Master Mode - 30 - DSP or μP MCLK BCLK LRCK SDTI SDTO MCKO pin 256fs (default) 128fs 64fs 32fs (default) [AK4673] 2007/10 ...
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... PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the AK4673 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output ...
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... The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4673 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “ ...
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... The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4673 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “ ...
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... EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4673 becomes EXT master mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The ...
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... System Reset When power-up, the AK4673 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC bits is “ ...
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... [AK4673 2007/10 ...
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... [AK4673 2007/10 ...
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... Don't Care Lch Data Figure 29. Mode 2 Timing - 38 - [AK4673 ...
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... Lch Data Figure 30. Mode 3 Timing MIX bit ADC Lch data x All “0” x Rch Input Signal x Lch Input Signal 0 Lch Input Signal 1 (L+R)/ [AK4673 ...
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... MIC/LINE Input Selector The AK4673 has input selector for MIC-Amp. When MDIF1 and MDIF2 bits are “0”, INL1-0 and INR1-0 bits select LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− pins respectively. In this case, full-differential input is ...
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... IN1+ pin 1k INL1 bit INL0 bit INR1 bit Table 22. MIC/Line In Path Select Example - 41 - ADC Lch ADC Rch These blocks are not available at PLL mode. AK4673 SDTO pin A/D INR0 bit Lch Rch 1 IN1+/− RIN2 1 LIN2 RIN2 [AK4673] 2007/10 ...
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... MIC Gain Amplifier The AK4673 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits 23). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. ...
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... Digital EQ/HPF/LPF The AK4673 has a wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” ...
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... Amplitude 2 − 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) 1 − tan (πfc/fs tan (πfc/fs) Amplitude 2 + 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs [AK4673] Phase (B+1)sin (2πf/fs) − (B−1)cos (2πf/fs) Phase (B−1)sin (2πf/fs) − (B+1)cos (2πf/fs) 2007/10 ...
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... Amplitude 2ACcos (2πf/fs 2Bcos (2πf/fs) =3000Hz, Gain=+8dB 2 fc Frequency − tan (πfc /fs =10 x /fs tan (πfc 1 Phase (AB−C)sin (2πf/fs) −1 θ(f) = tan (AB+C)cos (2πf/fs) 13 [AK4673] /fs) 2 /fs) 1 2007/10 ...
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... Table 30. ALC Zero Crossing Timeout Period - 46 - ALC Power-down Playback path Recording path Recording path Recording path (Table 28), the IVL and 0.375dB (default) 0.750dB 1.500dB 3.000dB 0.375dB 44.1kHz 8ms 2.9ms (default) 16ms 5.8ms 32ms 11.6ms 64ms 23.2ms [AK4673] (default) (Table 29). The (Table (default) 2007/10 ...
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... Table 32. ALC Recovery GAIN Step - 47 - (Table 28) during the wait time, the ALC 16kHz 44.1kHz 8ms 2.9ms (default) 16ms 5.8ms 32ms 11.6ms 64ms 23.2ms 128ms 46.4ms 256ms 92.9ms 512ms 185.8ms 1024ms 371.5ms 0.375dB (default) 0.750dB 1.125dB 1.500dB [AK4673] (Table 32) up (Table 30). 2007/10 ...
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... Table 33. Reference Level at ALC Recovery operation RFST1 bit Table 34. Fast Recovery Speed Setting (N/A: Not available) MS0670-E-01 GAIN(dB) +36.0 +35.625 +35. +30.375 +30.0 +29.625 : : −53.25 −53.625 −54.0 MUTE RFST0 bit Recovery Speed Step 0.375dB (default) 4 times (default) 8 times 16times N/A [AK4673] 2007/10 ...
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... Operation −4.1dBFS −4.1dBFS 01 Enable 0 Enable 32ms 11 23.2ms 32ms 011 23.2ms +30dB E1H +30dB +30dB E1H +30dB 1 step 00 1 step 1 step 00 1 step 4 times 00 4 times Enable 1 Enable (1) Addr=06H, Data=14H (2) Addr=08H, Data=E1H (3) Addr=09H&0CH, Data=E1H (4) Addr=0BH, Data=00H (5) Addr=07H, Data=21H [AK4673] 2007/10 ...
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... IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H MS0670-E-01 (Table 36). The IVOL value is changed at zero crossing or GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54 MUTE Table 36. Input Digital Volume Setting - 50 - [AK4673] (default) 2007/10 ...
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... ALC bit = “0”. MS0670-E-01 Disable Enable E1H(+30dB) C6H(+20dB) E1H(+30dB) E1(+30dB) --> F1(+36dB) (1) C6H(+20dB) E1(+30dB) --> F1(+36dB) Figure 36. IVOL value during ALC operation - 51 - [AK4673] Disable E1(+30dB) (2) C6H(+20dB) 2007/10 ...
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... De-emphasis Filter The AK4673 includes the digital de-emphasis filter (tc = 50/15μs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 37). ■ Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal bits are set to “01” (MIN Level), use a 47μF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale ...
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... Digital Output Volume The AK4673 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “ ...
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... Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0670-E-01 D VTM bit ( (2) Figure 38. Soft Mute Function - VTM bit ( [AK4673] 2007/10 ...
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... MIN/LIN3 pin VCOC/RIN3 pin LIN4/IN4+ pin RIN4/IN4− pin MS0670-E-01 AK4673 INL1-0 bits MIC-Amp MDIF1 bit INR1-0 bits MIC-Amp MDIF2 bit Lineout, HP-Amp Figure 39. Analog Mixing Circuit (Stereo Input [AK4673] ADC Lch ADC Rch These blocks are not available at PLL mode. 2007/10 ...
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... HPL/HPR 0dB +3.6dB Headphone-Amp Output Gain (typ LOUT/LOP pin, ROUT/LON pin HPL, HPR pins LOUT/LOP pin, ROUT/LON pin HPL, HPR pins LOUT/LOP pin, ROUT/LON pin HPL, HPR pins (default) LOUT/ROUT Output Gain (typ) (default) LOP/LON Output Gain (typ) (default) [AK4673] 2007/10 ...
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... Lineout, HP-Amp IN4+/IN4− LOUT/ROUT −6dB −4dB LOUT/ROUT Output Gain (typ) IN4+/IN4− LOP/LON 0dB +2dB LOP/LON Output Gain (typ) IN4+/IN4− HPL/HPR −6dB −2.4dB Headphone-Amp Output Gain (typ [AK4673] MIC-Amp Lch MIC-Amp Rch (default) (default) (default) 2007/10 ...
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... LOP/LON 0 +6dB 1 +8dB LOP/LON Output Gain (typ MIN HPL/HPR −20dB 0 −16.4dB 1 Headphone-Amp Output Gain (typ [AK4673] and Table 49 show the typical gain example LOUT/LOP pin, ROUT/LON pin HPL, HPR pin (default) = 20kΩ i (default) = 20kΩ i (default) = 20kΩ ...
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... Output Voltage (typ) 0dB 0.6 x AVDD +2dB 0.757 x AVDD Table 51. Stereo Line Output Volume Setting LOUT 1μF ROUT - 59 - LOUT pin ROUT pin LOUT/ROUT pin Pull-down to VSS1 (default) Normal Operation Fall down to VSS1 Rise up to VCOM (default) 220Ω 20kΩ [AK4673] 2007/10 ...
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... LOUT and ROUT pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=3.3V. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0670-E- ≥ [AK4673 ≥ 2007/10 ...
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... Figure 48. ROUT Mixing Circuit (AIN3 bit = “0”, LOVL bit = “0”) MS0670-E-01 LINL2 bit 0dB LINL4 bit 0dB MINL bit 0dB DACL bit DAC Lch 0dB RINR2 bit 0dB RINR4 bit 0dB MINL bit 0dB DACL bit DAC Rch 0dB - 61 - [AK4673 LOUT pin ROUT pin X 2007/10 ...
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... MICR3 bit 0dB *These blocks are not available at PLL mode. MIC-Amp Rch DAC Rch 0dB - 62 - LINL2 bit LINL4 bit M LINL3 bit LOUT pin I X DACL bit RINR2 bit RINR4 bit M RINR3 bit ROUT pin I X DACL bit [AK4673] 2007/10 ...
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... DAC Figure 51. Mono Line Output Gain Output Voltage (typ) +6dB 1.2 x AVDD +8dB 1.5 x AVDD Table 52. Mono Line Output Volume Setting Mode Power-down Power-save Normal Operation Normal Operation Hi-Z VCOM - 63 - LOP pin LON pin (default) LOP LON Hi-Z Hi-Z Hi-Z VCOM/2 Normal Operation Hi-Z VCOM Hi-Z [AK4673] (default) 2007/10 ...
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... PLL mode. MIC-Amp Lch RINR2 bit 0dB RINR4 bit 0dB MICR3 bit RINR3 bit 0dB *These blocks are not available at PLL mode. MIC-Amp Rch DACL bit DAC Lch 0dB DACL bit DAC Rch 0dB - 64 - [AK4673] M LOP/N pin LOP/N pin I X 2007/10 ...
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... Headphone-Amp oscillates. MS0670-E-01 0 0.6 x AVDD Table 54. Headphone-Amp Output Voltage τ = 100ms(typ), 250ms(max) (1) (2) (3) Table (Table 54). 1 0.91 x AVDD “0”: 500ms(max) (4) shows the cut off frequency and the output is 16Ω. Output powers are shown at L [AK4673] 2007/10 ...
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... When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, HP-Amp is powered-down and HPL/R pins are pulled-down to VSS2 by 200kΩ (typ). In this setting available to connect HP-Amp of AK4673 and external single supply HP-Amp by “wired OR”. In this mode, power supply current is 20μA(typ). ...
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... Figure 57. Wired OR with External HP-Amp LINH2 bit 0dB LINH4 bit 0dB MINH bit − 20dB DACH bit DAC Lch 0dB RINH2 bit 0dB RINH4 bit 0dB MINH bit − 20dB DACH bit DAC Rch 0dB - 67 - [AK4673] Headphone M I HPL pin HPR pin X 2007/10 ...
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... MICR3 bit 0dB *These blocks are not available at PLL mode. MIC-Amp Rch DAC Rch 0dB - 68 - LINH2 bit LINH4 bit M LINH3 bit HPL pin I X DACH bit RINH2 bit RINH4 bit M RINH3 bit HPR pin I X DACH bit [AK4673] 2007/10 ...
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... A/D Converter for Touch Screen The AK4673 incorporates a 12-bit successive approximation resistor (SAR) A/D converter for position measurement. The architecture is based on a capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (S/H) circuit. The SAR A/D converter output is a straight binary format as shown below: ■ ...
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... MS0670-E-01 X-Plate YP-Driver SW ON Y-Plate VREF+ AIN+ ADC VREF- AIN- YN-Driver Y-Position Measurement Differential Mode X-Plate (Top side) Y-Plate (Bottom side 4-wire Touch Screen Construction Figure 63 Axis Measurements - TSVDD X-Plate XP Y-Plate YP XN Touch Screen YN [AK4673] ) The XN 2007/10 ...
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... Rtouch = (Rxplate*Xposition/4096)*[(4096/Z1) – 1] – Ryplate*[1 – (Yposition/4096)] TSVDD YP-Driver VREF+ AIN+ ADC VREF- AIN- XN XN-Driver SWON YN a) Z1-Position Measurement MS0670-E-01 TSVDD YP-Driver SW ON Rtouch VREF+ ADC VREF- XN-Driver Z2-Position Measurement Figure 64 Pen Pressure Measurements - 71 - [AK4673 Rtouch AIN+ AIN 2007/10 ...
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... All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4673 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE) ...
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... The AK4673 will generates an acknowledge after each byte is received. In the read mode, the slave, AK4673 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmitting the data ...
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... Operations] The second byte that followed by address byte consists of the control command byte of the AK4673. The operational mode is determined by control command. The bit format is MSB first and 8 bits width. Control command is described in the Table 60. The AK4673 generates an acknowledge after each byte is received. A control command transfer is terminated by a STOP condition or Repeated Start condition generated by the master ...
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... A2-0 bit, PD0 bit, and MODE bit. Once sending command to fix the internal register after first power up, the state of the AK4673 is held on the known-condition of state to ensure that the AK4673 is going into desire mode to realize lowest mode. A command with PD0= “0” should be sent so that the AK4673 will be set in the lowest power down mode. ...
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... Control Command The control command, 8 bits, provided to the AK4673 via SDA, is shown in the following table. This command includes start bit, channel selection bit, power-down bit and resolution bit. The AK4673 latches the serial command at the rising edge of SCL. Refer to the detailed information regarding the bit order, function, the status of driver switch, ADC input as ...
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... A/D conversion is held on the next 12 SCL period (except MASTER ACK). After address byte is sent, the readout sequence starts with an acknowledge, which is the responce of the AK4673 when the address maches. The MSB data byte will follow (D11∼D4) then issued acknowledge by master. The LSB data byte (D3∼ ...
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... Pen Interrupt The AK4673 has a pen-interrupt function to detect the pen touch on the touch panel. This function will be used as the interrupt of the microprocessor. Pen interrupt function is enabled at power-down state. YN driver is on and this pin is connected to GND at the power down state. And the XP pin is pulled up via an internal resister (Ri), typically 10KΩ. If the touch plate is touched by pen or stylus, the current flows via < ...
Page 79
... HIGH defines a STOP condition (Figure The AK4673 can perform more than one byte write operation per sequence. After receiving of the third byte the AK4673 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred ...
Page 80
... READ Operations Set the R/W bit = “1” for the READ operation of the AK4673. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after receiving of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to generating a stop condition, the address counter will “ ...
Page 81
... F1A11 F1A10 F1A9 F1B4 F1B3 F1B2 F1B1 F1B11 F1B10 F1B9 PMMICR PMAINR2 PMAINL2 L4DIF MIX AIN3 RINR3 LINL3 RINR2 RINH3 LINH3 RINH2 [AK4673 PMADL PMPLL 0 MGAIN0 0 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 0 ...
Page 82
... PDN pin should be “L”. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0670-E- PMVCM PMMIN PMLO PMDAC [AK4673] D0 PMADL 0 2007/10 ...
Page 83
... When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1. MS0670-E- HPZ HPMTN PMHPL PMHPR (Table 23 M/S 0 MCKO DACL 0 PMMP [AK4673 PMPLL MGAIN0 0 1 2007/10 ...
Page 84
... MSBS (Table 6 and Table 7.) and MCKI Frequency Select (Table 18) (Table 18) (Table 10 MINL PLL0 BCKO 0 DIF1 BCKP FS2 FS1 (Table 12.) [AK4673 DIF0 0 D0 FS0 0 2007/10 ...
Page 85
... REF7 REF6 REF5 REF4 WTM1 WTM0 RFST1 (Table 30 LMAT1 LMAT0 RGAIN0 (Table 28 REF3 REF2 REF1 (Table 33.) [AK4673] D0 RFST0 0 D0 LMTH0 0 D0 REF0 1 2007/10 ...
Page 86
... IVL2 IVL1 IVR3 IVR2 IVR1 36 DVL3 DVL2 DVL1 DVR3 DVR2 DVR1 VBAT (Table 28 BST1 BST0 DEM1 [AK4673] D0 IVL0 IVR0 1 D0 DVL0 DVR0 DEM0 1 2007/10 ...
Page 87
... HPG: Headphone-Amp Gain Select 0: 0dB (default) 1: +3.6dB MS0670-E- INR1 INL1 HPG (Table 20) (Table 20) 54.) (Table - IVOLC HPM MINH MDIF2 MDIF1 INR0 INL0 [AK4673] D0 DACH PMADR 0 0 2007/10 ...
Page 88
... EQB11 EQB10 EQB9 EQC3 EQC2 EQC1 EQC11 EQC10 EQC9 F1A3 F1A2 F1A1 F1A11 F1A10 F1A9 F1B3 F1B2 F1B1 F1B11 F1B10 F1B9 [AK4673 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 2007/10 ...
Page 89
... Power down (default) 1: Power up PMAINL4: LIN4 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR4: RIN4 Mixing Circuit Power Management 0: Power down (default) 1: Power up MS0670-E- PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMMICR PMAINR2 PMAINL2 [AK4673] D0 PMMICL 0 2007/10 ...
Page 90
... LIN3 input signal is selected. (default) 1: MIC-Amp Lch output signal is selected. MICR3: Switch Control from MIC-Amp Rch to Analog Output 0: RIN3 input signal is selected. (default) 1: MIC-Amp Rch output signal is selected. MS0670-E- MICR3 MICL3 [AK4673 L4DIF MIX AIN3 LODIF 2007/10 0 ...
Page 91
... LOM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Stereo Line Output 0: Stereo Mixing (default) 1: Mono Mixing LOM: Mono Mixing from DAC to Stereo Line Output 0: Stereo Mixing (default) 1: Mono Mixing MS0670-E- LOM LOM3 RINR4 LINL4 [AK4673 RINR3 LINL3 RINR2 LINL2 2007/10 0 ...
Page 92
... RINH4: Switch Control from RIN4 pin to Headphone Output (without MIC-Amp) 0: OFF (default HPM3: Mono Mixing from MIC-Amp (or LIN3/RIN3) to Headphone Output 0: Stereo Mixing (default) 1: Mono Mixing MS0670-E- HPM3 RINH4 LINH4 [AK4673 RINH3 LINH3 RINH2 LINH2 2007/10 0 ...
Page 93
... Table - When the AK4673 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4673. - 0.1μF ceramic capacitor should be attached to each supply pins. The type of other capacitors is not critical. ...
Page 94
... All digital input pins should not be left floating. - When AIN3 bit = “1”, PLL is not available. - When the AK4673 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4673. ...
Page 95
... TSVDD are supplied separately, the power-up sequence is not critical. The PDN pin should be held to “L” upon power-up. The PDN pin should be set to “H” after all power supplies are powered-up. In case that the pop noise should be avoided at line output and headphone output, the AK4673 should be operated by the following recommended power-up/down sequence. ...
Page 96
... PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (6) The AK4673 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation starts. (7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”. ...
Page 97
... After Power Up: The PDN pin “L” The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. ...
Page 98
... After Power Up: The PDN pin “L” The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period. ...
Page 99
... After Power Up: The PDN pin “L” The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) DIF1-0 and FS1-0 bits should be set during this period. ...
Page 100
... BICK pin <Example> (1) After Power Up: The PDN pin “L” The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output. (2) MCKI should be input. (3) After DIF1-0 and FS1-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output. ...
Page 101
... Registers set-up sequence at ALC At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4673 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H) ...
Page 102
... At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4673 is PLL mode, DAC and Headphone-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” ...
Page 103
... ROUT pin <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). When the AK4673 is PLL mode, DAC and Stereo Line-Amp should be powered-up in consideration of PLL lock time after the sampling frequency is changed. (2) Set up the path of “DAC (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “ ...
Page 104
... PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) Addr:01H, Data:00H (2) Stop the external clocks Example Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz (1) Addr:01H, Data:00H (2) Stop the external clocks [AK4673] 2007/10 ...
Page 105
... Figure 97. Clock Stopping Sequence (5) - 105 - Example Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) Stop the external clocks Example Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) Stop the external MCKI [AK4673] 2007/10 ...
Page 106
... BGA (Unit: mm) 5.0 ± 0.1 ■ Material & Lead finish Package molding compound: Interposer material: Solder ball material: MS0670-E-01 PACKAGE 57 - φ 0.3 ± 0.05 φ 0. 0.08 S Epoxy BT resin SnAgCu - 106 - [AK4673 0.5 0.5 2007/10 B ...
Page 107
... XXXX: Date code (4 digit) Pin #A1 indication REVISION HISTORY Reason Page Contents First Edition Error 15 Filter Characteristics Collection TVDD1=2.5 ~ 3.6V, TSVDD=3.3V → TVDD1 = TSVDD = 2.5 ~ 3.6V IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2) - 107 - [AK4673] in any safety, life support, or Note1) 2007/10 ...