ak4671 AKM Semiconductor, Inc., ak4671 Datasheet - Page 51

• Manufacturer Part Number: ak4671
• Description: Stereo Codec With Mic/rcv/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

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When power-up, the AK4671 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAL
and PMDAR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the
ADC digital data outputs of both channels are forced to a 2’s complement, “0”. The ADC output reflects the analog input
signal after the initialization cycle is complete. When PMDAL or PMDAR is “1”, the ADC does not require an
initialization cycle.
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Four types of data formats are available and can be selected by setting the DIF1-0 bits
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4671 in master mode, but must be input to the AK4671 in slave mode.
In modes 1, 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge
(“↑”).
In Modes 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0666-E-00
DIF1
Mode
System Reset
Audio Interface Format
0
0
1
2
3
DIF0
DIF1 bit
0
0
0
1
1
MSBS
0
0
1
1
DIF0 bit
0
1
0
1
BCKP
0
1
0
1
Table 17. Audio Interface Format in Mode 0
MSB of SDTO is output by the rising edge (“↑”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“↓”) of the
first BICK after the rising edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“↑”) of the
falling edge (“↓”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the falling edge (“↓”) of the
BICK just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“↓”) of the
rising edge (“↑”) of the first BICK after the rising edge
(“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the
BICK just after the output timing of SDTO’s MSB.
I
SDTO (ADC)
MSB justified
MSB justified
2
S compatible
DSP Mode
Table 16. Audio Interface Format
Audio Interface Format
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I
MSB justified
LSB justified
SDTI (DAC)
2
S compatible
DSP Mode
≥ 32fs
≥ 32fs
≥ 32fs
≥ 32fs
BICK
(Table
(Table
17).
16). In all modes, the serial
Figure 49
Figure 50
Figure 51
Table 17
Figure
Figure 45
Figure 46
Figure 47
Figure 48
Figure
[AK4671]
(default)
(default)
2007/10