ak4651 AKM Semiconductor, Inc., ak4651 Datasheet
ak4651
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ak4651 Summary of contents
Page 1
... CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4651 is connected with AC’97 controller (CPU) via AC-Link. The AK4651 is available in a very small 57pin BGA, utilizing less board space than competitive offerings. ...
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... ASAHI KASEI 4. System Clock: 24.576MHz, 12MHz, 3.6864MHz 5. Sampling Rate: 48kHz, 44.1kHz, 32kHz, 24kHz, 22.05kHz, 16kHz, 11.025kHz, 8kHz 6. Power Management 7. Audio & Control I/F: AC-Link I −30 ∼ 85°C 9. Power Supply: 2.7V ∼ 3.6V (typ. 3.3V) 10. Package: 57pin BGA (5mm x 5mm) 11. AK4650 Pin Compatible MS0503-E- [AK4651] 2006/04 ...
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... DATT DAC SMUTE MIX MIX PMLIN PMAUX Volume Volume Volume MIX PMBP MDT/RIN MPE/LIN BEEP MIN MOUT2 AUXIN+ Figure 1. Block Diagram - 3 - [AK4651] DVSS2 INTN RESETN SYNC Audio BITCLK CPU SDATAIN SDATAOUT PLL1 PR5 VRA XTO/PLL0 PR5 PLL XTI/MCKI VCOC1 VCOC2 AUXIN- ...
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... ASAHI KASEI Ordering Guide −30 ∼ +85°C AK4651VG AKD4651 Evaluation board for AK4651 Pin Layout BEEP/IN2 AVDD 8 VCOC1 VCOC2 AVSS 7 TEST2 AVDD2 6 TEST3 TEST4 5 TEST5 AVSS2 4 TEST7 TEST6 3 TEST9 TEST8 2 TEST10 INTN XTO/PLL0 1 NC DVDD1 XTI/MCKI ...
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... HPL O Lch Headphone Amp Output Pin H7 O Mono Line Negative Output Pin MOUT− J7 MOUT+ O Mono Line Positive Output Pin H8 AIN I Analog Input Pin No Connect Pin internal bonding. This pin should be open or connected to the ground. MS0503-E-00 PIN/FUNCTION Function - 5 - [AK4651] 2006/04 ...
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... Output 1 Pin for Loop Filter of PLL Circuit B8 VCOC2 O This pin should be connected to DVSS with a resistor (10kΩ) and a capacitor (4.7nF) in series. Note: All input pins except analog input pins should not be left floating (XTI/MCKI, PLL0, SDATAOUT, SYNC, RESETN and PLL1 pins). MS0503-E-00 Function - 6 - [AK4651] 2006/04 ...
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... This pin should be floating. Headphone Jack Detect Interrupt Output Pin B2 INTN O This pin should be pulled up via a 100kΩ resistor. Test 10 Pin A2 TEST10 - This pin should be connected to the ground. No Connect Pin internal bonding. This pin should be open or connected to the ground. MS0503-E-00 Function - 7 - [AK4651] 2006/04 ...
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... Pin Name MIN, MOUT2, MUTET, HDT, SPP, SPN, HPR, HPL, MOUT−, MOUT+, AIN, MICOUT, MDT/RIN, Analog MPE/LIN, EXT/MIC+, INT/MIC−, MPI, AUXIN−, AUXIN+, BEEP, INTN Digital XTO MS0503-E-00 Setting These pins should be open. This pin should be open [AK4651] 2006/04 ...
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... AVDD, DVDD and HVDD is larger than 0.3V, the power supply current at power down mode increases (see Note 28). When the power supplies are partially powered OFF, the AK4651 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. DVDD1 and DVDD2 should be same voltage. ...
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... Vout = 0.6 x AVDD(typ)@MOGN2-0 bits = “111” at single-ended Output. MS0503-E-00 ANALOG CHARACTERISTICS min 1. 0.15 250 5 0 0.168 =20kΩ, DAC → MOUT+/MOUT− pins, MOGN2-0 bits = +6dB L 3. [AK4651] typ max Units 30 40 kΩ + 0.099 - Vpp 2.2 2. kΩ 0.20 0.23 V 500 750 kΩ kΩ ...
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... Note 22. Maximum Input Voltage depends on AVDD voltage, internal feedback resistance (Rf) and external input resistance (Ri). Vin = 0.6 x AVDD (typ). MS0503-E-00 min =16Ω, DAC → HPL/HPR pins, DATT=0dB 0.045 1. [AK4651] typ max Units 0.82 - Vrms 0.41 0.50 Vrms 0 Ω 300 pF - 2.31 V ...
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... Note 28. All digital input pins are fixed to DVDD or DVSS. When the voltage difference among AVDD, DVDD and HVDD is larger than 0.3V, the power supply current at power down mode increases. MS0503-E-00 min typ - 1. 0.5 1.5 - +12 −34 1. 0.5 1.5 - +12 −34 2 [AK4651] max Units - Vpp 55 kΩ 2 Vpp 55 kΩ 110 kΩ 2 µA 100 2006/04 ...
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... Note 31. These frequency responses scale with fs high-level and low frequency signal is input, the analog output clips to the full-scale. MS0503-E-00 FILTER CHARACTERISTICS Symbol min 29 ∆ 25 16.14 - 11. [AK4651] typ max Units - 18.9 kHz 21.8 - kHz kHz 23 kHz ±0 17.0 - 1/fs µ 1 6 21.3 kHz 24.0 - kHz - - kHz ±0. 16.8 - 1/fs ± ...
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... Input Leakage Current INTN “L” level output voltage (100kΩ Pull-Up) Note 32. When AC coupled capacitor is connected to MCKI pin. MS0503-E-00 DC CHARACTERISTICS Symbol min VIH 70%DVDD VIL - VAC 50%DVDD VOH DVDD−0.4 VOL - Iin - VOLP - - 14 - [AK4651] typ Max Units - - V - 30%DVDD 0.4 V ±10 µ ...
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... Tdelay - Trise_din - Tfall_din - Trise_dout - Tfall_dout - Trst_low 1.0 Trst2clk - Trst2clk - Trst2clk - Trst2clk - Tsync_high 1.0 Trst2clk - Tsync2clk - Tsync2clk - Tsync2clk - Ts2_pdwn - Tsetup2rst 15.0 Thold2rst 100 Toff - Tlow - - 15 - [AK4651] typ max Units 24.576 - MHz 3.6864 - MHz 12 - MHz - 60 % 12.288 - MHz 81 kHz µs 19.5 - (240 cycle) (Tbclk) µ ...
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... Figure 4. SYNC Timing Tsetup Thold Figure 5. Setup and Hold Timing Trise_din 90%DVDD SDATAIN 10%DVDD Trise_dout 90%DVDD SDATAOUT 10%DVDD Figure 6. Signal Rise and Fall Times - 16 - [AK4651] VIH VIL = Tmclkl x Fmclk x 100 50%DVDD VIH VIL VIH VIL VIH VIL VIH VIL Tfall_din 90%DVDD ...
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... BITCLK MS0503-E-00 Trst_low Trst2clk Figure 7. Cold Reset Timing Tsync_high Tsync2clk Figure 8. Warm Reset Timing Slot Slot Ts2_pdwn Write to 0x26 Data PR4=1 Don’t care Tsetup2rst Thold2rst Tlow Figure 10. Activate Test Mode Timing - 17 - [AK4651] VIL VIH VIH VIL VIH HI-Z VIL Toff 2006/04 ...
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... ASAHI KASEI Master Clock Source The AK4651 requires a master clock (MCLK). This master clock is input to the AK4651 by the following three methods: (1) Connect a X’tal oscillator between XTI and XTO pins. (2) Input an external CMOS-level clock to the XTI pin. (3) Input an external clock whose amplitude is greater than 50%DVDD to the XTI pin with AC coupling. ...
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... PLL1 = "L" PLL1 = "L" AK4651 MCKPD = "0" PR5 = "0" 25kΩ (typ) PLL1 = "H" PLL1 = "H" AK4651 MCKPD = "0" PR5 = "0" 25kΩ (typ) PLL1 = "L" PLL1 = "L" AK4651 - 19 - [AK4651] 2006/04 ...
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... MCLK and SYNC must be present whenever the ADC or DAC is operating (PR0 = PR1 = PR3 = PR4 = PR5 = “0”). If these clocks are not provided, the AK4651 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, the ADC and DAC must be placed in the power-down mode by setting PR0-6 bits. ...
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... The AK4651 supports these discrete frequencies. When any other codes is written in this register, the AK4651 operates at the sampling rate rounded to the closest one in Table 4 by decoding only D15-12 bits. If D15-12 = 5H, the AK4651 operates at 22.05kHz or 24kHz when D11 = “0” or “1”, respectively (Table 5). ...
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... PU(Note 37 PMHPL PMSPK PD PD PMMIC PD PD PMLIN PD PD PMAUX PD PD PMMO PD PD PMBPM Table 6. Power Management - 22 - [AK4651] PR5 = “1” PR6 = “1” VRA PD PU PMHPL/R PD PMSPK PMSPK PMMIC PMMIC PMLIN PMLIN PMAUX PMAUX ...
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... MSEL bit +20dB/0dB IPGA with ALC EXT pin MICOUT pin The AK4651 has the following functions for Mic Input. (1) 2 Inputs Selector. The switch configure is controlled by MDIF and MSEL bits (Table 9). st (2) 1 MIC Amplifier with +20dB gain, The gain can be selected ON/OFF by MGAIN bit (Table 10). ...
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... ASAHI KASEI MIC Input Selector AK4651 has mic input selector in front of mic amp. MSEL bit selects internal or external mic (Figure 16). When MDIF bit = “1”, INT and EXT pins become MIC− and MIC+ pins, respectively, and differential input is available (Figure 17). ...
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... ASAHI KASEI MIC Gain Amplifier The AK4651 has a Gain Amplifier for Microphone input. The gain is 0dB or +20dB, selected by the MGAIN bit. The typical input impedance is 30kΩ. MIC Power The MPI and MPE pins supply power for the Microphone. These output voltages are 2.2V (typ) and load resistance is 2kΩ ...
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... ASAHI KASEI Manual Mode The AK4651 becomes a manual mode at ALC1 bit = “0”. The mode is used in the case shown below. (1) After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) (2) When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. ...
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... Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms Table 18. Zero Crossing Timeout Period - 27 - [AK4651] Default Default 44.1kHz 11µs Default 23µs 45µs 91µs 44.1kHz 2.9ms Default 5.8ms 11.6ms 23.2ms 2006/04 ...
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... ASAHI KASEI (2) ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4651 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation (Table 19). If the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset Level” ...
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... Enable Table 22. Example of the ALC1 setting Example: * The value of IPGA should be the same or smaller than REF’ [AK4651] fs=16kHz fs=44.1kHz Data Operation Data Operation −4dBFS −4dBFS Don’t use 00 Don’t use 0 Enable ...
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... ASAHI KASEI De-emphasis Filter The AK4651 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 23). DEM1 Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 24). If the BST1-0 bits are set to “ ...
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... ASAHI KASEI Digital Attenuator The AK4651 has a channel-independent digital attenuator (128 levels, 0.5dB step, Mute). The attenuation level of each channel can be set by the ATTL/R6-0 bits (Table 25). When the DATTC bit = “1”, the ATTL6-0 bits control both Lch and Rch attenuation levels. When the DATTC bit = “0”, the ATTL6-0 bits control Lch level and ATTR6-0 bits control Rch level ...
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... If the soft mute is cancelled within the cycle of setting the TM1-0 bits, the attenuation is discounted and returned to 0dB(the set value). TM1 MS0503-E-00 TM 1-0 bit ( (2) Figure 20. Soft Mute Function TM0 Cycle 0 0 1024/fs Default 0 1 512/ 256/ 128/fs Table 27. Soft Mute Time Setting - 32 - [AK4651] ( 2006/04 ...
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... ASAHI KASEI AUX Input AK4651 AUXIN+ pin AUXIN− pin AUX input is a differential input. The AK4651 has a volume for AUX Input. This Volume is controlled by GN3-0 bits as shown in Table 28. The switching noise occurs when GN3-0 bits are changed. AUXMT 0 1 Table 28. AUX Input Gain Setting (x: Don’t care) ...
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... When LNMP bit is “1”, MPE pin becomes LIN pin. When RNMD bit is “1”, MDT pin becomes RIN pin. LIN/RIN is single-ended input. The AK4651 has a volume for Stereo Line Input. This Volume is controlled by GL4-0 and GR4-0 bits as shown in Table 28. The switching noise occurs when GL4-0 or GR4-0 bits are changed. ...
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... Speaker-amp without gain. The internal feedback resistance is 20kΩ ± 30%. When BPMT bit is “1”, BEEP input is muted. AK4651 Ri BEEP pin MS0503-E-00 BPMHP bit Rf BPMSP bit Figure 23. Block Diagram of BEEP pins (Rf = 20kΩ ± 30 [AK4651] HP Lch -20dB HP Rch SP 2006/04 ...
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... Figure 24. Mono Output Mode MOUT+/MOUT− pin Power-down Mute VCOM Normal operation Normal operation Table 30. Mono Output Setting GAIN (dB) STEP +6.0 +3.0 +0.0 −3.0 3dB −6.0 −9.0 −12.0 −15.0 Table 31. Mono Output Gain Control - 36 - [AK4651] AK4651 MOUT+ pin MOUT− pin Hi-Z Default Default 2006/04 ...
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... Headphone-amp power-down (PMHPL, PMHPR bits = “0”). The outputs are HVSS. If the power supply is switched off or Headphone-amp is powered-down before the common voltage goes to HVSS, some pop noise occurs. MS0503-E-00 100k x C (typ) 200k x C (typ) Table 32. Headphone-Amp Rise/Fall Time = 100kΩ x 1µF = 100ms(typ (1) (2) ( [AK4651 (4) = 100k x r 2006/ ...
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... HP-AMP AK4651 Figure 26. External Circuit Example of Headphone R [Ω] C [µF] BOOST=OFF 220 0 100 100 6.8 47 100 16 47 Table 33. Relationship of external circuit, output power and frequency response MS0503-E- Headphone 16Ω fc [Hz] fc [Hz] BOOST=MIN 2.7V 45.2 17 27.9 99.5 42 69.8 28 13.7 148.5 74 49.7 19 7.0 105 [AK4651 Output Power [mW] 3.0V 3.3V 34.5 41.7 17.0 20.5 8.6 10.4 2006/04 ...
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... HPMT PMHPR PMSPK SPPS [AK4651] HDT pin “L” (pulled-down by external 2.2k) “H” (pulled-up by internal 100k) HP-Amp Power Down Power Down Power UP SPK-Amp Power Down Power Save Power UP Power Down Power Save 2006/04 ...
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... When the SPPS bit is “1”, the Speaker-amp is power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4651 is powered-down, pop noise can be also reduced in power-save-mode. ...
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... Figure 29. DAC input – Speaker output relationship (HVDD=3.3V, ALC2 bit = “1”) MS0503-E-00 ALC2 Limiter operation ALC2 Recovery operation +1.8dBV 2048/fs = 46.4ms@fs=44.1kHz 2/fs = 45µs@fs=44.1kHz 2/fs = 181µs@fs=11.025kHz 512/fs = 46.4ms@fs=11.025kHz Diabled Enabled (Timeout = 2048/fs) 0.5dB step (Limitter) (Recovery) (ALC2=OFF [AK4651] −2dBV 1dB step DAC In 2006/04 ...
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... Mono Out Audio CODEC AK4651 ADC Mic In Side Tone ATT HP DAC Amp HP Out Aux In Mono Out Figure 31. Phone Audio CODEC AK4651 ADC Mic In Side Tone ATT HP DAC Amp HP Out Aux In Mono Out Figure 32. Recording/Playback & Phone - 42 - [AK4651] CPU CPU CPU 2006/04 ...
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... AC-Link Power-down The AK4651 controls the AC-link power-up/down by PR4 and PR5 bits. When PR4 bit is “1”, BITCLK and SDATAIN go to “L”, but X’tal oscillator still operates. When PR5 bit is “1”, BITCLK and SDATAIN go to “L”, and X’tal oscillator is powered-down. PLL power-up/down is controlled by VRA bit. PR4 bit = “ ...
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... If a slot is “Tagged” invalid the responsibility of the source of the data (the AK4651 for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s active time. ...
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... Note that SDATAOUT and SDATAIN data is delayed one BITCLK because AC’97 controller causes SYNC signal high at a rising edge of BITCLK which initiates a frame. “Output” stream means the direction from AC’97 controller to the AK4651, and “Input” stream means the direction from the AK4651 to AC’97 controller. ...
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... Bit 12 (Slot 3 valid bit): Validity of slot 3 (DAC Left data input) Bit 11 (Slot 4 valid bit): Validity of slot 4 (DAC Right data input) If each bit is “0”, the AK4651 ignores the slot indicated by “0”. On the other hand, if each bit is “1”, the slot is valid. Bit 10-0 should be “0”. ...
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... Address Table 41. AK4651 Addressing: Slot 0 Tag Bits [Slot 1]: Command Address Port Slot1 gives the address of the command data, which is given in the slot 2. The AK4651 has 30 valid registers of 16bit data. See “Mixer Registers”. BIT_CLK Bit19 Bit18 Bit17 SDATA_OUT “ ...
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... PCM Playback Left Channel (16bit) The AK4651 uses the playback (DAC) data format in slot 3 for left channel. Playback data format is MSB first. Data format is 16bits 2’s complement. AC’97 controller should stuff bit 3-0 with “0”. If valid bit (slot 3) in the slot 0 is invalid (“ ...
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... Note 39. The above Read sequence is done as response for previous frames read command. That is, if the previous frame is the Write Command, AK4651 outputs bit14 =”0”, bit13 =”0” and slot 1&2 = All”0”, if there is no SLOTREQ. Note 40. The Bits 14 and 13 in Slot 0 is independent of the SLOTREQ Bits 11 and 10 in Slot 1 which the AK4651 supports. ...
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... Status Address Port Audio input frame slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slot 1 valid bit and slot 2 valid bit in the slot 0 had been tagged “valid” by the AK4651.) BIT_CLK ...
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... PCM Record Left Channel Record (ADC) data format is MSB first. Data format is 2’s complement. As the resolution of the AK4651 is 16bit, lower 4 bits are ignored. If ADC block is powered down, slot 3 valid bit in the slot 0 is invalid (“0”), and data is output as all “0”. ...
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... AK4651 is ready for normal operation. At that time, VRA bit is its default value (“0”). Therefore, fs=48kHz and TS=1/fs=20.83µs. Status bit in the slot 0 is “0” (not ready) when the AK4651 is in RESET period (“L” initialization process. After initialization cycles, the status bit goes to “1” (ready). ...
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... ASAHI KASEI Warm Reset The AK4651 initiates warm reset process by receiving a single pulse on the SYNC. The AK4651 clears PR4 bit and PR5 bit in the Power-down Control Register. However, warm reset does not influence PR0-3, 6 and 7 bits in Power-down Control Register. Note 41. SYNC signal should synchronize with BITCLK after AK4651 starts to output BITCLK clock. ...
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... ATS ATTM ATTS2 [AK4651 Default 0 0 0030H 0 0 8000H 0 0 8000H MOGN1 MOGN0 8000H 0 0 0000H 0 0 8000H GN1 GN0 8008H IPGA1 IPGA0 8008H GR1 GR0 8808H ...
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... GN4-0: AUX Input Volume Control (Table 28) Default: “08H” (0dB) MIC Volume (0EH) MICMT: Mic Input Mute Control (Table 14) 0: Mute OFF 1: Mute ON (Default) MGAIN: MIC-Amp Gain Control (Table 10) 0: 0dB (Default) 1: +20dB IPGA5-0: IPGA Control (Table 14) Default: “08H” (0dB) MS0503-E- [AK4651] 2006/04 ...
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... ON When LOOP bit is “1”, VRA bit should be “0”. MSEL: Internal/External MIC Select (Table 9 at MDIF bit = “0”) 0: Internal MIC (Default) 1: External MIC MDIF: Differential MIC Input Select (Table 9) 0: Single-ended Input (Default) 1: Differential Input MS0503-E- [AK4651] 2006/04 ...
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... OFF(Default). PLL is powered-down Audio Sample Rate control Registers (2CH, 32H) SR15-0: Sample Rate Control for DAC (2CH) and ADC (32H) (Table 4, Table 5) Default: “BB80H”(48kHz) These Sample Rate setting is done at VRA bit = “1”. MS0503-E- [AK4651] 2006/04 ...
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... MIC Power is ON for Internal MIC. MPWRI bit is enabled when PMMIC bit = “1”. MPWRE: External MIC Power Supply Control (Table 12) 0: OFF (Default) 1: MIC Power is ON for External MIC. MPWRE bit is enabled when PMMIC bit = “1”. MS0503-E- [AK4651] 2006/04 ...
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... AUXL: AUXIN to Headphone/Speaker-Amp Enable 0: OFF (Default DAHS: DAC to Headphone/Speaker-Amp Enable 0: OFF 1: ON (Default) LNMP: LIN/MPE pin Selection 0: MPE pin (Default) 1: LIN pin RNMD: RIN/MDT pin Selection 0: MDT pin (Default) 1: RIN pin HPM: Mono Output Select of Headphone 0: Stereo (Default) 1: Mono [(L+R)/2] MS0503-E- [AK4651] 2006/04 ...
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... WTM1-0 bits set a period of recovery operation when any limiter operation does not occur during the ALC1 operation. ZTM1-0: ALC1 zero crossing timeout selection (Table 18) Default: “00” (128/fs) When the IPGA performs zero crossing or timeout, the IPGA value is changed by the µP WRITE operation, ALC1 recovery operation or ALC1 limiter operation (ZELMN bit = “0”). MS0503-E- [AK4651] 2006/04 ...
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... Volume Control (68H) ATTS2-0: Volume control of signal from IPGA to Headphone/Speaker-Amp (Table 7) Default: “2H” (−12dB) ATTM: Volume control of signal from IPGA to Mono Line Output (Table 8) 0: 0dB (Default) 1: −4dB ATS: Digital attenuator transition time setting (Table 26) Default: “0” (531/fs) MS0503-E- [AK4651] 2006/04 ...
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... DTHPJ: Headphone jack insertion detection result (Read only, Table 34) 0: Headphone jack is not inserted. 1: Headphone jack is inserted. Slot Control (72H) SLOT: Headphone jack insertion detection result output select on Slot 12 0: Disable (Default) 1: Enable Vendor ID (7CH, 7EH) “A(41H), K(4BH), M(4DH), 16(10H)” (Read only) MS0503-E- [AK4651] 2006/04 ...
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... TEST9 TEST10 NC 100k 10 + 10u 0.1u 24.576MHz Note 45. AVSS, DVSS and HVSS of the AK4651 should be distributed separately from the ground of external controllers. Note 46. All input pins except for internal pull-down pins should not be left floating. MS0503-E-00 SYSTEM DESIGN Internal MIC + BEEP AVDD VCOM ...
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... TSVDD are usually supplied from the system’s analog supply. If AVDD, DVDD and HVDD are supplied separately, the correct power up sequence should be observed. AVSS, DVSS, HVSS and TSVSS of the AK4651 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board ...
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... ASAHI KASEI 57pin BGA (Unit: mm) 5.0 ± 0.1 Material & Lead finish Package molding compound: Interposer material: Solder ball material: MS0503-E-00 PACKAGE 57 - φ 0.3 ± 0.05 φ 0. 0.5 S 0.08 S Epoxy BT resin SnAgCu - 65 - [AK4651 0.5 2006/04 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0503-E-00 MARKING 4651 XXXX XXXX: Date code (4 digit) Pin #1 indication Revision History Page Contents IMPORTANT NOTICE - 66 - [AK4651] 2006/04 ...