ak7746 ETC-unknow, ak7746 Datasheet - Page 25

• Manufacturer Part Number: ak7746
• Description: Audio With 5-channel 24-bit Input
• Manufacturer: ETC-unknow

6Ah
6Ch
6Eh
60h
62h
64h
66h
68h
Command
W
(2) Control registers
[MS0369-E00]
[ASAHI KASEI]
Code
The control registers can be set via the microcomputer interface in addition to the control pins. These 8 registers consist of 7-bit data
however; SCLK always needs to be a16-bit clock (Command Code 8-bits, Data 8-bits). Each register is set after the last D0 data is
written. For the value to be written in the control registers see the description of the interface with microcomputer. The following
table describes the control register map.
These control registers are initialized by INIT_RESET =”L”, but these are NOT initialized by S_RESET ="L”.
7Ah
7Ch
7Eh
70h
72h
74h
76h
78h
R
1.
2.
3.
4.
5.
CONT0
CONT1
CONT2
CONT3
CONT4
CONT5
CONT6
CONT7
Name
CONT0 can be set only at system reset ( INIT_RESET =”H” & S_RESET =”L”).
It is recommended to set CONT1~CONT2, CONT4~CONT7 at system reset.
When changing the selector switch of CONT3, a click noise may occur. The selector switchs are set during the writing
timing of the CONT3 D0 (SCLK ↑).
The control registers can be read during run time.
The default setting is initialized by initial reset ( INIT_RESET =”L”).
SWAD1_N
OUT4E_N
ASEL2[2]
SWQM2
DFS[2]
DRAM
JX2_E
TEST
D7
SWSDIN4_
OUT3E_N
ASEL2[1]
CLKS[1]
SWQM1
DFS[1]
JX1_E
RM
D6
N
OUTA2E_N
SWSDIN3_
OUT2E_N
ASEL2[0]
BANK[1]
CLKS[0]
DFS[0]
JX0_E
D5
N
TEST: for TEST (input 0), (X: it ignores input data, but should input 0).
- 25 -
OUTA1E_N
SWSDIN2_
OUT1E_N
BANK[0]
SSDIN4
SWQ4
TEST
DIFS
D4
N
CLKOE_N
SWSDIN1
ASEL1[2]
PSADM
CMP_N
SSDIN3
DIF[1]
SWQ3
D3
SWADM3_
ASEL1[1]
SWQMD
PSAD2
DIF[0]
SWQ2
TEST
SS[1]
D2
N
SWADM2_
ASEL1[0]
SETCK
PSAD1
SWQ1
SS[0]
TEST
TEST
D1
N
D0
X
X
X
X
X
X
X
X
[AK7746]
2004/12
0000 000X
0000 000X
0000 000X
0000 000X
0000 000X
0000 000X
0000 000X
0000 000X
Default