ak7746 ETC-unknow, ak7746 Datasheet - Page 32

• Manufacturer Part Number: ak7746
• Description: Audio With 5-channel 24-bit Input
• Manufacturer: ETC-unknow

6Ch
Command
W
7) CONT6 : CLKO setting & Internal path setting ( See. 3 Block diagram)
Recommend this register changing at system reset state ( S_RESET =”L” ).
Note1) MCLK is the internal master clock. MCLK is changed by inputting XTI frequency. Normally, MCLK is 36.864MHz or
Note 2) CLKS Mode 3 output data is determined by CONT0 SETCK(D1).
Note 3) It takes 12ms(max) until the clock comes out following INIT_RESET release.
Note 4) When this control register changes, noise may occur on CLKO. Once CLKO comes out, it can not stop
Note) Underlines of the
[MS0369-E00]
[ASAHI KASEI]
Code
CLKS
Mode
0: Normal operation
0: Normal operation
0: Normal operation
0
1
2
3
D7 : TEST
D4 : SWQ4 SDOUT4 Output select
D3 : SWQ3 SDOUT3 Output select
D2 : SWQ2 SDOUT2 Output select
D1 : SWQ1 SDOUT1 Output select
D0 : Always input 0
1: Through outputs of SDIN4.
1: Through outputs of SDIN3.
1: Through outputs of SDIN2.
0: Normal operation
1: Through outputs of SDIN1.
D6,D5 : CLKS[1],CLKS[0] CLKO Output select
7Ch
R
Note that it includes output delay.
Note that it includes output delay.
Note that it includes output delay.
Note that it includes output delay.
unless CLKE_N is set to 1 or a reset is initialized (while the clock is supplied)
33.8688MHz. See (5) 1) Master clock select table.
0: Normal operation
1: TEST Mode ( Do NOT use. )
CLKS[1]
CONT6
Name
0
0
1
1
CLKS[0]
TEST
~
D7
0
1
0
1
mean default setting.
CLKS[1]
D6
MCLK × 2/9
MCLK/2
MCLK/3
SETCK
CLKO
CLKS[0]
D5
- 32 -
@36.864MHz
CONT0(D1)
18.432MHz
12.288MHz
8.192MHz
SWQ4
MCLK
D4
SWQ3
D3
@33.8688MHz
16.9344MHz
11.2896MHz
CONT0(D1)
7.5264MHz
SWQ2
MCLK
D2
SWQ1
D1
D0
×
[AK7746]
2004/12
0000 000X
Default