ltm9002 Linear Technology Corporation, ltm9002 Datasheet
ltm9002
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ltm9002 Summary of contents
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... Fixed Gain: 8dB, 14dB, 20dB or 26dB 50Ω, 200Ω or 400Ω Input Impedance n Integrated Bypass Capacitance, No External Components Required n 66dB SNR Up to 140MHz Input (LTM9002-AA) n 76dB SFDR Up to 140MHz Input (LTM9002-AA) n Auxiliary 12-Bit DACs for Gain Adjustment n Clock Duty Cycle Stabilizer n Single ...
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... Digital Input Voltage (Except AMPSHDN) ................. –0. Digital Input Voltage (AMPSHDN) ..............................–0. Digital Output Voltage ................–0.3V to (OV Operating Temperature Range LTM9002C................................................ 0°C to 70°C LTM9002I .............................................–40°C to 85°C Storage Temperature Range ...................–65°C to 125°C ORDER INFORMATION LEAD FREE FINISH TRAY ...
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... DNL Differential Linearity Error l The denotes the specifi cations which apply over the full operating = 25°C. Unless otherwise noted. (Note 3) A CONDITIONS DC, LTM9002- 140MHz IN Channel A, DC (LTM9002-LA 15MHz IN Channel B, DC (LTM9002-LA 15MHz MAX, (Note 3) IN External Reference Both Channels, f ...
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... Input, LTM9002-AA 15MHz Input, LTM9002-LA 140MHz Input, LTM9002-AA 15MHz Input, LTM9002-LA The l indicates specifi cations which apply over the full operating = 25°C. (Not applicable for LTM9002-LA) (Note The denotes the specifi cations which apply over the full operating = 25°C. A ...
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... O l The denotes the specifi cations which apply over the full operating temperature = 25°C. (Note 7) CONDITIONS DAC Powered Up, Both Amplifi ers Enabled, LTM9002-AA Both Amplifi ers Enabled, LTM9002-LA AMPSHDN = 3V, DAC Powered Down LTM9002-AA LTM9002-LA DAC Powered Up, LTM9002-AA LTM9002-LA ...
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... INCM ADCSHDN = 0V, unless otherwise noted The denotes the specifi cations which apply over the full operating temperature = 25°C. (Note 6) (Not applicable for LTM9002-LA) CONDITIONS LTM9002-AA LTM9002-LA Duty Cycle Stabilizer Off (Note 6), LTM9002-AA Duty Cycle Stabilizer On (Note 6), LTM9002-AA Duty Cycle Stabilizer Off (Note 6), LTM9002-AA ...
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... B – – – – – – – – – LTM9002 – – 9002 TD01 – – – – – – ...
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... LTM9002 TIMING DIAGRAMS SCK SDI CS/LD TYPICAL PERFORMANCE CHARACTERISTICS (LTM9002-AA) Differential Non-Linearity (DNL) vs Output Code 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 16384 OUTPUT CODE 9002 G01 Input Impedance vs Frequency 60 55 MAGNITUDE PHASE ...
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... G08 Integral Non-Linearity (INL), Best Fit vs Output Code 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 1024 2048 3072 OUTPUT CODE LTM9002 = 74MHz FREQUENCY (MHz) 9002 G07 = 140MHz FREQUENCY (MHz) 9002 G09 SNR vs Frequency (Channel A) 72 ...
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... SENSE = V (Channel –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –100 –120 FREQUENCY (MHz) (LTM9002-LA) 8 MAGNITUDE PHASE 100 1000 FREQUENCY (MHz) 9002 G14 64k Point FFT 15MHz, IN –1dBFS, SENSE = –10 – ...
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... The specifi ed operating range is 2.85V to 3.465V. The voltage on this pin provides power for the amplifi er stage and auxiliary DACs only and is internally bypassed to GND. Note that LTM9002-LA does not have auxiliary DACs. V (Pins E7, E8): Analog 3V Supply for ADC. The specifi operating range is 2 ...
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... An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input range of ±V SENSEB Digital Inputs (Not Connected on LTM9002-LA) CS/LD (Pin F3): Serial Interface Chip Select/Load Input for Auxiliary DAC. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specifi ...
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... OFB (Pin E12, LTM9002-LA): Overfl ow/Underfl ow Output. High when an overfl underfl ow has occurred on channel B. DA0 – DA13 (Refer to Pin Confi guration Table): Channel A ADC Digital Outputs. DA13 is the MSB for LTM9002-AA; DA11 is the MSB for LTM9002-LA. Pin Confi guration (LTM9002-AA) 1 ...
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... Functional Block Diagram (Only One Channel is Shown ADC FILTER DRIVER – IN VOLTAGE AMPSHDN REFERENCE VOLTAGE REFERENCE DAC SENSE *OFA AND OFB ON LTM9002-LA 14 PIPELINED ADC SECTIONS INPUT 1st 2nd 3rd 4th S/H SHIFT REGISTER AND ERROR CORRECTION REFH REF BUFFER DIFF REF AMP CS/LD SDI SCK GND ...
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... SNRJITTER = –20log (2π) • f Crosstalk The amount of signal coupled from one channel into the other. This is measured by applying a full-scale sinusoidal input on channel A, shorting the inputs of channel B and taking the ratio of the signal powers in an FFT. LTM9002 • JITTER 9002f 15 ...
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... LTM9002 OPERATION Description The LTM9002 is an integrated system in a package (SiP) that includes two high-speed 14-bit A/D converters, matching networks, anti-aliasing fi lters and two low noise, differen- tial amplifi ers with fi xed gain. These amplifi ers need not be the same, so that the gains and input impedances of the two channels are different ...
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... AMPLIFIER OPERATION The amplifi ers used in the LTM9002 are low noise and low distortion fully differential op amps/ADC drivers with operation from DC to 2GHz (–3dB bandwidth). The ampli- fi ...
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... LTM9002 OPERATION reference adjusts the ADC span proportionately; see Adjusting the full-scale input range. Powering down the auxiliary DAC disables the ADC span trim control. When the auxiliary DAC is powered down, connect SENSE external reference. DD Power-On Reset The auxiliary DACs clear the outputs to zero-scale when power is fi ...
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... OPERATION LTM9002 9002f 19 ...
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... LTM9002 APPLICATIONS INFORMATION INPUT SPAN The LTM9002 is confi gured with a given input span and input impedance. With the amplifi er gain and the ADC input network described above for LTM9002-AA, the full-scale input range of the driver circuit is 0.1V recommended ADC input span is achieved by tying the SENSE pin to V ...
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... F06 Input Range The input range can be set based on the application. The 0.1V input range (LTM9002-AA) will provide the best SNR performance while maintaining excellent SFDR. The lower /2) input range will have slightly better SFDR performance, but IN the SNR will degrade by 5dB ...
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... SENSE pin which results in a 18μV step for the input span. In this case, the SENSE pin may be bypassed with 0.1μF capacitor. The auxiliary DACs must be subsequently set each time the LTM9002 is powered up. 1.25V REF 2.5k 1V (OPEN CIRCUIT, ...
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... Maximum and Minimum Conversion Rates The maximum conversion rate for the LTM9002-AA is 125Msps and the LTM9002-LA is 65Msps. The lower limit of the sample rate is determined by the droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capaci- tors. The specifi ...
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... OGND, isolated VDD voltages will also help reduce interference LTM9002 0.1μ 43Ω OGND 9002 F12 Figure 12. Digital Output Buffer DD 0 ...
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... V 2’s Complement DD Overfl ow Bit For LTM9002-AA, when OF outputs a logic high the con- verter is either overranged or underranged on channel A or channel B. Note that both channels share a common OF pin disabled when channel sleep or nap mode. For LTM9002-LA, OFA and OFB indicate either condition for the respective channel ...
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... Heat Transfer Most of the heat generated by the LTM9002 is transferred through the bottom-side ground pads. For good electrical and thermal performance critical that all ground pins are connected to a ground plane of suffi cient area with as many vias as possible ...
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... DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 108 SYMBOL TOLERANCE aaa 0.15 bbb 0.10 eee 0.05 LTM9002 DETAIL A 13.97 BSC 10.16 BSC 1.27 BSC PADS ...
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... LTM9002 RELATED PARTS PART NUMBER DESCRIPTION LT1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifi er/Driver LTC2205 16-Bit, 65Msps ADC LTC2206 16-Bit, 80Msps ADC LTC2207 16-Bit, 105Msps ADC LTC2208 16-Bit, 130Msps ADC LTC2240-12 12-Bit, 170Msps, 2.5V ADC, LVDS Outputs LTC2241-12 12-Bit, 210Msps, 2 ...