atr2434 ATMEL Corporation, atr2434 Datasheet - Page 18

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atr2434

Manufacturer Part Number
atr2434
Description
Wirelessusb 2.4-ghz Dsss Radio Soc - Atmel Corporation
Manufacturer
ATMEL Corporation
Datasheet
Table 15. Receive SERDES Valid B
Table 16. Transmit Interrupt Enable
18
Bit
7:0
Bit
7:4
3
2
1
0
Addr: 0x0D
7
7
Name
Reserved
Underflow
Overflow
Done
Empty
Name
Valid
Addr: 0x0C
ATR2434 [Preliminary]
Description
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates
that the corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES
Data B register (Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register
(Reg 0x0C).The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed
by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Description
These bits are reserved and should be written with zeros.
The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the
Transmit SERDES Data register (Reg 0x0F)
1 = Underflow interrupt enabled
0 = Underflow interrupt disabled
An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F)
does not have any data.
The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit
SERDES Data register (0x0F).
1 = Overflow interrupt enabled
0 = Overflow interrupt disabled
An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg
0x0F) before the preceding data has been transferred to the transmit shift register.
The Done bit is used to enable the interrupt that signals the end of the transmission of data.
1 = Done interrupt enabled
0 = Done interrupt disabled
The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data
and there is no more data for it to transmit.
The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is
empty.
1 = Empty interrupt enabled
0 = Empty interrupt disabled
The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit
buffer and it's safe to load the next byte
6
6
Reserved
5
5
REG_RX_VALID_B
4
REG_TX_INT_EN
4
Valid
Underflow
3
3
Overflow
2
2
Done
1
1
Default: 0x00
Default: 0x00
4822C–ISM–09/04
Empty
0
0

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