atr2434 ATMEL Corporation, atr2434 Datasheet - Page 19

• Manufacturer Part Number: atr2434
• Description: Wirelessusb 2.4-ghz Dsss Radio Soc - Atmel Corporation
• Manufacturer: ATMEL Corporation

Table 17. Transmit Interrupt Status
4822C–ISM–09/04
Note:
Bit
7:4
3
2
1
0
Note:
7
Name
Reserved
Underflow
Overflow
Done
Empty
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be imple-
mented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For
example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only.
1. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be
Addr: 0x0E
implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6).
For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only.
Description
These bits are reserved. This register is read-only.
The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data
register (Reg 0x0F) has occurred.
1 = Underflow Interrupt pending
0 = No Underflow Interrupt pending
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An
underflow occurs when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit
SERDES Data register (Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This
bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data
register (0x0F) has occurred.
1 = Overflow Interrupt pending
0 = No Overflow Interrupt pending
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow
occurs when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous
data has been sent. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
The Done bit is used to signal the end of a data transmission.
1 = Done Interrupt pending
0 = No Done Interrupt pending
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This
will only assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit
Interrupt Status register (Reg 0x0E)
The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.
1 = Empty Interrupt pending
0 = No Empty Interrupt pending
This IRQ will assert when the transmit SERDES is empty. When this IRQ is asserted it is ok to write to the
Transmit SERDES Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear
this IRQ. It will be set when the data is loaded into the transmitter, and it is ok to write new data.
6
Reserved
5
REG_TX_INT_STAT
4
Underflow
3
ATR2434 [Preliminary]
Overflow
2
Done
1
Default: 0x00
Empty
0
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