ispgdx160a Lattice Semiconductor Corp., ispgdx160a Datasheet

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ispgdx160a

Manufacturer Part Number
ispgdx160a
Description
In-system Programmable Generic Digital Crosspoint
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
• HIGH PERFORMANCE E
• ispGDX OFFERS THE FOLLOWING ADVANTAGES
• FLEXIBLE ARCHITECTURE
Copyright © 2002 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
ispgdx_11
Features
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
— Three Device Options: 80 to 160 Programmable I/O
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
— Space-Saving TQFP, PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
— PCI Compliant Output Drive
— 5V Power Supply
— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
— Low-Power: 40mA Quiescent Icc
— Balanced 24mA Output Buffers with Programmable
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E
— 100% Tested
— In-System Programmable
— Lattice ISP or JTAG Programming Interface
— Only 5V Power Supply Required
— Change Interconnects in Seconds
— Reprogram Soldered Devices
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock Input Pins (two or four) or
— Up to 4:1 Dynamic Path Selection
— Programmable Output Pull-up Resistors
— Outputs Tri-state During Power-up (“Live Insertion”
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
Pins
Switch Emulation
Test
Slew Rate Control
Programmable Clocks from I/O Pins (from 20 up to
40)
Friendly)
2
CMOS Technology
2
CMOS
®
TECHNOLOGY
1
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of system-
level digital signal routing and interface requirements
including:
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clock-
to-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Functional Block Diagram
Description
Boundary
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
• Programmable Control Signal Routing
• Board-Level PCB Signal Routing for Prototyping or
Control
Scan
(e.g. 4:1 High-Speed Bus MUX)
(e.g. Interrupts, DMAREQs, etc)
Programmable Bus Interfaces
Cells
I/O
ispGDX
Generic Digital Crosspoint
Global Routing
In-System Programmable
I/O Pins D
I/O Pins B
(GRP)
Pool
®
Family
November 2003
Cells
I/O
Control
ISP

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ispgdx160a Summary of contents

Page 1

... Copyright © 2002 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com ...

Page 2

... Lattice de- vices in hot swap environments can be downloaded from the Lattice web site at www.latticesemi.com. ispGDX DEVICE ispGDX80A ispGDX120A 1 100-Pin TQFP 176-Pin TQFP/ 160-Pin PQFP 2 ispGDX160A 120 160 ...

Page 3

Architecture The ispGDX architecture is different from traditional PLD architectures, in keeping with its unique application fo- cus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI no programmable logic ...

Page 4

Applications The ispGDX family architecture has been developed to deliver an in-system programmable signal routing solu- tion with high speed and high flexibility. The devices are targeted for three similar but distinct classes of end- system applications: Programmable, Random Signal ...

Page 5

Applications (Cont.) Figure 3. Address Demultiplex/Data Buffering XCVR I/OA I/OB OEA OEB Address Latch D Q CLK Figure 4. Data Bus Byte Swapper XCVR D0-7 I/OA I/OB OEA OEB XCVR D8-15 I/OA I/OB OEA OEB Figure 5. Four-Port Memory Interface ...

Page 6

Absolute Maximum Ratings Supply Voltage V ................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...

Page 7

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions TEST CONDITION A 160Ω Active High B ...

Page 8

External Timing Parameters TEST 1 PARAMETER # COND Data Propagation Delay from any I/O pin to any I/O pin Data Propagation Delay from MUXsel Inputs to any Output sel f – 3 Clock ...

Page 9

Internal Timing Parameters 2 PARAMETER # Inputs t 21 Input Buffer Delay io GRP t 22 GRP Delay grp MUX t 23 I/O Cell MUX A/B/C/D Data Delay muxd t 24 I/O Cell MUX A/B/C/D Data Select muxs Register t ...

Page 10

Switching Waveforms VALID INPUT MUXSEL (I/O INPUT) t sel DATA (I/O INPUT) VALID INPUT t pd COMBINATORIAL I/O OUTPUT Combinatorial Output OE (I/O INPUT) t dis COMBINATORIAL I/O OUTPUT I/O Output Enable/Disable CLK (I/O INPUT) Clock Width ...

Page 11

Development System The ispLEVER Development System supports ispGDX design using a VHDL or Verilog language syntax. From creation to in-system programming, the ispLEVER sys- tem is an easy-to-use, self-contained design tool. Features • VHDL and Verilog Synthesis Support Available ...

Page 12

Table 3. I/O Shift Register Order DEVICE SDI/TDI, I/O B10 .. B19, I C19, I D9, RESET, Y1/TOE, Y0, I B0, I/O A19.. A0, ispGDX80A I/O D19 .. D10, SDO/TDO SDI/TDI, I/O B15 .. ...

Page 13

Figure 7. Boundary Scan I/O Register Cell SCANIN M (from U previous X cell Shift DR Figure 8. Boundary Scan State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 TCK TMS or TDI TDO tsu = ...

Page 14

... Output/Output Pin – Serial data output during ISP programming or Boundary Scan mode. GND Ground (GND) VCC Vcc – Supply voltage (5V Connect pins are not to be connected to any active signals, VCC or GND. Signal Locations: ispGDX160A Signal TOE 178 RESET 185 Y0, Y1, Y2, Y3, 75, 76, 180, 181 BSCAN/ispEN 183 ...

Page 15

... I/O Locations: ispGDX160A 208 272 Signal PQFP BGA Signal PQFP BGA I/O A32 I I I/O A33 I I/O A34 I I/O A35 I I/O A36 I I/O A37 I I/O A38 I I/O A39 I I/O B0 I I/O A10 13 G2 I/O B2 I/O A11 14 G1 I/O B3 I/O A12 16 H2 I/O B4 I/O A13 18 J4 I/O B5 I/O A14 19 J3 ...

Page 16

... Signal Configuration: ispGDX160A ispGDX160A 272-Ball BGA Signal Diagram I/O I/O I I/O I/O I D11 I/O I/O I/O I/O I C39 I/O I/O I/O D GND NC 1 VCC C36 C38 D0 I/O I C33 C37 I/O I/O I/O F C35 VCC C30 C32 I/O I/O I/O I/O G C28 C29 ...

Page 17

... Pin Configuration: ispGDX160A ispGDX160A 208-Pin PQFP (with Heat Spreader) Pinout Diagram Control Data 1 — VCC CLK I I MUXsel1 I MUXsel2 I — GND CLK I I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I ...

Page 18

Signal Locations: ispGDX120A Signal TOE 150 RESET 156 Y0, Y1, Y2, Y3, 63, 64, 152, 153 BSCAN/ispEN 154 TDI/SDI 69 TCK/SCLK 68 TMS/MODE 67 TDO/SDO 66 GND 8, 17, 27, 37, 50, 65, 77, 91, 101, 110, 120, 129, 144, ...

Page 19

Pin Configuration: ispGDX120A ispGDX120A 176-Pin TQFP Pinout Diagram Control Data 1 1 — NC — — VCC 4 CLK I I MUXsel1 I MUXsel2 I ...

Page 20

Pin Configuration: ispGDX120A ispGDX120A 160-Pin PQFP Pinout Diagram Control Data — VCC 1 CLK I I MUXsel1 I MUXsel2 I — GND 6 CLK I ...

Page 21

Signal Locations: ispGDX80A Signal 100-Pin TQFP Y1/TOE RESET 89 BSCAN/ispEN 35 TDI/SDI 39 TCK/SCLK 36 TMS/MODE 86 TDO/SDO 85 GND 6, 18, 29, 45, 56, 68, 79, 95 VCC 12, 37, 62, 88 I/O Locations: ispGDX80A Signal ...

Page 22

Pin Configuration: ispGDX80A ispGDX80A 100-Pin TQFP Pinout Diagram Control Data CLK I I MUXsel1 I MUXsel2 I CLK I GND 6 — ...

Page 23

... X XXXX X Grade Blank = Commercial Package Q208 = PQFP (with Heat Spreader) T176 = TQFP Q160 = PQFP B272 = BGA T100 = TQFP COMMERCIAL ORDERING NUMBER ispGDX160A-5Q208 ispGDX160A-5B272 ispGDX160A-7Q208 ispGDX160A-7B272 ispGDX120A-5T176 ispGDX120A-5Q160 ispGDX120A-7T176 ispGDX120A-7Q160 ispGDX80A-5T100 ispGDX80A-7T100 23 0212/ispGDX PACKAGE 208-Pin PQFP 272-Ball BGA 208-Pin PQFP 272-Ball BGA ...

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