ispgal22v10c-7lk Lattice Semiconductor Corp., ispgal22v10c-7lk Datasheet

no-image

ispgal22v10c-7lk

Manufacturer Part Number
ispgal22v10c-7lk
Description
In-system Programmable E2 Cmos Pld Generic Array Logic?
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPGAL22V10C-7LK
Manufacturer:
ACTEL
Quantity:
101
• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)
• HIGH PERFORMANCE E
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
• E
• TEN OUTPUT LOGIC MACROCELLS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically Eras-
able (E
system programmable 22V10 device. E
speed (<100ms) erase times, providing the ability to reprogram or
reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by al-
lowing the Output Logic Macrocell (OLMC) to be configured by the
user. The ispGAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices. The stan-
dard PLCC package provides the same functional pinout as the
standard 22V10 PLCC package with No-Connect pins being used
for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
isp22v10_04
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
Description
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5 ns Maximum from Clock Input to Data Output
— UltraMOS
— Fully Function/Fuse-Map/Parametric Compatible
— In-System Programmable Logic
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
2
CELL TECHNOLOGY
Resistor on Board (ispGAL22V10C Only)
with Bipolar and CMOS 22V10 Devices
2
) floating gate technology to provide the industry's first in-
®
Advanced CMOS Technology
2
CMOS
®
TECHNOLOGY
2
technology offers high
1
MODE
Functional Block Diagram
Pin Configuration
MODE
SCLK
SDO
I
I
I
I
I
I
SDI
5
7
9
1 1
In-System Programmable E
1 2
4
ispGAL22V10
PROGRAMMING
I/CLK
Top View
LOGIC
1 4
I
I
I
I
I
I
I
I
I
I
I
2
PLCC
1 6
2 8
ispGAL22V10
1 8
2 6
2 3
2 1
2 5
1 9
Generic Array Logic™
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
MODE
SCLK
I/CLK
GND
PRESET
RESET
10
12
14
16
16
12
10
14
I
I
I
I
I
I
I
I
I
I
8
8
1
7
14
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
Top View
2
ispGAL
SSOP
22V10
CMOS PLD
August 2004
28
22
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI

Related parts for ispgal22v10c-7lk

ispgal22v10c-7lk Summary of contents

Page 1

... Features • IN-SYSTEM PROGRAMMABLE™ (5-V ONLY) — 4-Wire Serial Programming Interface — Minimum 10,000 Program/Erase Cycles — Built-in Pull-Down on SDI Pin Eliminates Discrete Resistor on Board (ispGAL22V10C Only) • HIGH PERFORMANCE E 2 CMOS ® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 111 MHz — ...

Page 2

... Part Number Description ispGAL22V10C Device Name Speed (ns Low Power Power Specifications ispGAL22V10 ...

Page 3

Output Logic Macrocell (OLMC) The ispGAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and ...

Page 4

Registered Mode ACTIVE LOW Combinatorial Mode ACTIVE LOW Specifications ispGAL22V10 ...

Page 5

Logic Diagram/JEDEC Fuse Map 0000 0044 . . . 0396 0440 . . . . 0880 3 0924 . . . . . 1452 4 1496 . . . . . . 2112 5 2156 . ...

Page 6

... Supply Current f toggle 1) The leakage current is due to the internal pull-up on all pins (except SDI on ispGAL22V10C). See Input Buffer section for more information. 2) The leakage current is due to the internal pull-down on the SDI pin (ispGAL22V10C only). See Input Buffer section for more information. ...

Page 7

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Capacitance (T = 25° 1.0MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications ispGAL22V10C Specifications ispGAL22V10 Over Recommended Operating Conditions MIN. MAX. 6.5 111 111 MAXIMUM* UNITS COM COM ...

Page 8

Switching Waveforms INPUT or I/O FEEDBACK COMBINATORIAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis OUTPUT Input or I/O to Output Enable/Disable CLK (w/o fdbk) Clock Width INPUT or I/O ...

Page 9

Descriptions max with External Feedback 1/( Note: fmax with external feedback is cal- culated from measured tsu ...

Page 10

... All input and I/O pins (except SDI on the ispGAL22V10C) also have built-in active pull-ups result, floating inputs will float to a TTL high (logic 1). The SDI pin on the ispGAL22V10C has a built-in pull-down to keep the device out of the programming state if the pin is not actively driven. However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground ...

Page 11

... Circuit (Except SDI on ispGAL22V10C) Vcc Vref ESD Protection Circuit PIN ESD Protection Circuit Pull-down Resistor (SDI on ispGAL22V10C Only) Input Specifications ispGAL22V10 Vcc (min Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" Device Pin Reset to Logic " ...

Page 12

... Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0.25 -0.5 -0. Number of Outputs Switching Delta Tpd vs Output Loading Output Loading (pF) Specifications ispGAL22V10 Normalized Tco vs Vcc 1 ...

Page 13

... Typical AC and DC Characteristic Diagrams Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vcc 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications ispGAL22V10 Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) ...

Page 14

Notes ...

Related keywords