tea5764uk-n2 NXP Semiconductors, tea5764uk-n2 Datasheet - Page 22
tea5764uk-n2
Manufacturer Part Number
tea5764uk-n2
Description
Fm Radio + Rds
Manufacturer
NXP Semiconductors
Datasheet
1.TEA5764UK-N2.pdf
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Philips Semiconductors
TEA5764UK_2
Product data sheet
Fig 7. Operation and timing of pause detection according to levels set in
(1) The reference level is defined in kHz, but is internally transformed to mV e.g. 22.5 kHz = 75 mV; 1 kHz = 3.3 mV.
(2) The actual PSCO signal behaves as shown in the top diagram, in the bottom diagram it is assumed that all samples are
t
taken at peaks of the audio signal resulting in PSCOn.
np(min)
integrator
PDFLAG
PSCOn
output
audio
9.1.4.7 Frequency ready flag
> 5 ms.
audio signal
(2)
0
PSCO
In
and 1 16 ms pause. Therefore on average the pause detector has measured 16 ms 12
ms + 16 ms = 20 ms pause time and hence a pause will be detected.
The PSCOn signal goes directly to the software port. The PDFLAG is set by the integrator
and goes to the bus. The interrupt line is triggered by the PDFLAG.
The frequency ready flag bit is set to logic 1 when the automatic tuning has finished a
search, a preset or an RDS AF update. This bit is described in
FRRFLAG is cleared by a read of byte1R.
t
1
Equation
6, the pause detector has measured 1
t
pause
Rev. 02 — 9 August 2005
t
2
t
audio
t
pause
Table 38
+ reference level "PL" [mV] (1)
0
pause
no pause
16 ms ‘pause’, 8
reference level "PL"
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table 4
TEA5764UK
PT x 2341
audio present
no audio present
and
1.5 ms ‘no pause’
FM radio + RDS
001aac795
Table
5. The
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