mt8980dpr1 Zarlink Semiconductor, mt8980dpr1 Datasheet
mt8980dpr1
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mt8980dpr1 Summary of contents
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... ISO-CMOS ST-BUS MT8980DE MT8980DP MT8980DPR MT8980DP1 MT8980DE1 MT8980DPR1 Description This VLSI ISO-CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight serial inputs and outputs consist kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream ...
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... STo4 STi5 STo5 37 STi6 36 STo6 STi7 35 STo7 VDD 34 VSS R/W Figure 2 - Pin Connections Description 2 Zarlink Semiconductor Inc. Data Sheet 1 40 CSTo 2 39 ODE STo0 STo1 5 36 STo2 6 35 STo3 7 34 STo4 8 33 STo5 9 32 STo6 ...
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... The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key device being the MT8980 chip. MT8980D Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT8980s to be constructed. It also controls the CSTo pin. All ST-BUS timing is derived from the two signals C4i and F0i. MT8980D 4 Zarlink Semiconductor Inc. Data Sheet ...
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... ST-BUS input or output streams. MT8980D A1 A0 HEX ADDRESS • • • • • • • • • Figure 3 - Address Memory Map 5 Zarlink Semiconductor Inc. Data Sheet LOCATION Control Register * † Channel 0 † Channel 1 • • • † Channel 31 ...
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... ST-BUS channel 8 bits 7-0. MT8980D (unused) Memory Stream Select Address Bits DESCRIPTION Figure 4 - Control Register Bits 6 Zarlink Semiconductor Inc. Data Sheet Bits 1 0 ...
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... MT8980D No Corresponding Memory - These bits give 0s if read DESCRIPTION Figure 5 - Connection Memory High Bits Stream Channel Address Address Bits Bits DESCRIPTION Figure 6 - Connection Memory Low Bits 7 Zarlink Semiconductor Inc. Data Sheet Per Channel Control Bits ...
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... Figure 7 - Example of Typical Interface between 8980s and 8964s for Simple Digital Switching MT8980D originating from the bottom MT8980, which generates the C STo0 STi0 STo0 STi0 Line Interface Circuit with 8964 Filter/Codec System 8 Zarlink Semiconductor Inc. Data Sheet , and ST- R MT8964 Line Driver Filter/Codec and Wire Converter Signalling Logic ...
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... Repeated for Lines 2 to 255 STi0-7 8 Line Interface Circuit with Codec (e.g.8964) 8980 #1 STi0/7 STo0/7 8980 #2 STi0/7 STo0/7 8980 #3 STi0/7 STo0/7 8980 #4 STi0/7 STo0/7 9 Zarlink Semiconductor Inc. Data Sheet Line 1 • • • Repeated for Lines 2 to 255 Line 256 OUT 0/7 OUT 8/15 ...
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... Delay through the address decoder requires the VMA signal to be used twice to remove glitches. The MEK6802D3 board uses a 10 KΩ pullup on the MR pin, which would have to be incorporated into the circuit if the board was replaced by a processor. MT8980D 10 Zarlink Semiconductor Inc. Data Sheet ...
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... STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 0V VSS 510 Ω DTA CS 0V C4i 0V F0i 0V 0V 100pF 11 Zarlink Semiconductor Inc. Data Sheet A15 A14 A13 HCT 0V 5 138 VMA ...
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... Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 -0 °C -65 +150 unless otherwise stated. Units Test Conditions ° ...
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... CTT t 20 FPS t 0.020 FPH t 244 FPW Channel 31 Bit o Figure 12 - Frame Alignment 13 Zarlink Semiconductor Inc. Data Sheet S1 is open circuit except when testing output levels or high impedance states switched when testing output SS levels or high impedance states. Max. Units ...
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... OED XCH t 75 110 XCD t -40 -20 SIS t 90 SIH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet FPS t FPH Units Test Conditions KΩ*, C =150 =150 =150 pF ...
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... MT8980D Bit Cell Boundary 2.0V C4i 0.8V t SOH 2.4V STo0 to 0.4V STo7 STo0 2. STo7 0.4V STo0 2.4V to 0.4V STo7 2.4V CSTo 0.4V Figure 14 - Serial Outputs and External Control 2.0V ODE 0.8V 2.4V STo0 * to 0.4V STo7 t OED Figure 15 - Output Driver Enable 15 Zarlink Semiconductor Inc SAZ t SZA t SOH t SAA t XCH t XCD * t OED Data Sheet ...
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... DHT RDZ t 0 CSH t 0 RWH t 0 ADH AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet t SIH Units Test Conditions =150 cycles C4i cycles ns 1 cycles C4i cycles 1 cycles ...
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... DS 0.8V 2.0V CS 0.8V t CSS 2.0V R/W 0.8V t RWS 2. 0. ADS 2.4V * DTA 0.4V 2.4V (Read) 2.0V (Write 0.8V (Read 0.8V (Write) D0 MT8980D t AKD t RDS t t FWS SWD Figure 17 - Processor Bus 17 Zarlink Semiconductor Inc. Data Sheet t CSH t RWH t ADH t AKH * t DHT * t RDZ ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...