mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet
mt8986al1
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... CMOS ST-BUS Multiple Rate Digital Switch MT8986AE MT8986AP MT8986AL MT8986APR MT8986AP1 MT8986APR1 MT8986AL1 MT8986AE1 Description The Multiple Rate Digital Switch (MRDX upgraded version of Zarlink's MT8980D Digital Switch (DX pin compatible with the MT8980D and retains all of its functionality. This device is designed to ...
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... AD0 13 28 AD1 AD2 AD3 AD4 AD5 AD6 19 22 DS/RD AD7 R/W\ PIN DIP Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. Data Sheet 33 STo3 32 STo4 31 STo5 30 STo6/A6 29 STo7/A7 28 VSS 27 AD0 26 AD1 25 AD2 24 AD3 23 AD4 44 PIN QFP ...
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... Address 3-5 / Input Streams 11-13 (Input). When non-multiplexed CPU bus is 16-18 19-21 13-15 A3-5/ STi11-13 selected, these lines provide the A3-A5 address lines to MT8986 internal registers. When 16x8 switching configuration is selected (in 44 pin only), then these pins are ST-BUS serial inputs receiving data at 2.048 Mb/s. MT8986 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Output Drive Enable (Input). This is the output enable input for the STo0 ODE STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input is high each channel may still be put into high impedance by using per-channel control bits in Connect Memory High. MT8986 Description 4 Zarlink Semiconductor Inc. Data Sheet ...
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... By using Zarlink Message mode capability, the microprocessor can access input and output time-slots on a per channel basis to control external circuits or other ST-BUS devices. The MT8986 automatically identifies the polarity MT8986 Description 5 Zarlink Semiconductor Inc. Data Sheet ...
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... If an output channel is set to high-impedance, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel control, all channels on the TDM outputs can be placed in high impedance by pulling the ODE input pin LOW. This overrides the individual per-channel programming by the Connect Memory High bits. MT8986 6 Zarlink Semiconductor Inc. Data Sheet ...
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... SCB bits as shown in Table 8 (see IMS register). In case of different I/O rates (DMO bit HIGH), the switching configuration is always non-blocking with different number of I/O streams which is defined by the IDR and ODR bits (see IMS register). MT8986 7 Zarlink Semiconductor Inc. Data Sheet For example, if the FR pulse ...
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... Only 2 input x 2 output stream configuration is available for 8.192 Mb/s, allowing a 256 x 256 channel non-blocking switch matrix to be implemented. To enable this operation, the IDR bits should be programmed to select 8.192 Mb/s rates and the SCB bits have no effect. At 8.192 Mb/s, every input and output stream provides 128 time-slots per MT8986 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Number of Input Matrix x Output Channel Capacity Streams 8x4 256x256 Non-Blocking 8x2 256x256 Non-Blocking 4x8 256x256 Non-Blocking 2x8 256x256 Non-Blocking 9 Zarlink Semiconductor Inc. Data Sheet Variable/ Constant Input/Output throughput Streams Used Delay Selection STi0-7/STo0-7 Yes STi0-15/STo0-7 No STi0-9/STo0-9 Yes STi0-7/STo0-3 ...
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... Table 3a shows the MT8986 throughput delay for each data rate operation. Input Rate m < n 2.048 Mb/s 32-(n-m) t.s. 4.096 Mb/s 64-(n-m) t.s. 8.192 Mb/s 128-(n-m) t.s. Table 3a - Variable Throughput Delay Values for Identical I/O Rate Applications n= input channel, t.s. = time-slot MT8986 Output Channel (# m) m=n, n+1, n+2 m= n+3, n+4 m t.s. m-n t.s. m t.s. m-n+64 t.s. m-n + 128 t.s. m-n+128 t.s. 10 Zarlink Semiconductor Inc. Data Sheet m=n+5, .. n+8 m > n+8 m-n t.s. m-n t.s. m-n t.s. m-n t.s. m-n+128 t.s. m-n t.s. ...
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... IN: input time-slot (from 1 to 64) OUT: output time-slot (from 1 to 64) d=[128 + (128 - IN) + (OUT - 1)]; (expressed in # time-slots) 8.192 Mb/s time-slot: 0.975 µs IN: input time-slot (from 1 to 128) OUT: output time-slot (from 1 to 128) 11 Zarlink Semiconductor Inc. Data Sheet 6, 7 dmin=(2x 2Mb/s t.s.)+ (1x 8Mb/s t.s.) dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 8Mb/s t.s.) ...
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... The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream Address bits. The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory to be chosen, and the Stream Address bits define an internal memory subsections corresponding to input or output ST-BUS streams. MT8986 12 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 5 - Address Memory Map 13 Zarlink Semiconductor Inc. Data Sheet Location Control Register Interface Mode Select Register Stream Pair Select Register Frame Input Offset Register Channel 0* Channel 1* • • Channel 31* Channel 32** Channel 33** • ...
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... STA bits used to STA bits used to select subsections of select subsections of the Data the Connection Memory Memory STA2, STA1, STA0 STA1, STA0 14 Zarlink Semiconductor Inc. Data Sheet 0s STA1 STA0 Input Address pins used to select individual Connection and Data Memory positions ...
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... A4, A3, A2, A1, A0 STA2, STA1, A6, A4, A3, A2, A1, A0 STA0 STA2, STA1, A7, A6, A4, A3, A2, A1, A0 A4, A3, A2, A1, A0 STA0 15 Zarlink Semiconductor Inc. Data Sheet Input Address pins used to select individual Connection and Data Memory positions within the selected subsection A4, A3, A2, A1, A0 A6, A4, A3, A2, A1, A0 ...
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... For Different I/O data rate applications, this bit is ignored. MT8986 IDR0 ODR1 ODR0 SCB1 SCB0 DESCRIPTION IDR0 Input Rate 0 0 2.048 Mb 4.096 Mb 8.192 Mb reserved ODR0 Output Rate 0 2.048 Mb/s 1 4.096 Mb/s 0 8.192 Mb/s 1 reserved Figure 4 - IMS Register Description 16 Zarlink Semiconductor Inc. Data Sheet 1 0 CLKM ...
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... Non Blocking Nibble Switching - 8 inputs x 4 outputs - Blocking inputs x 4 outputs - Blocking inputs x 4 outputs - Non-Blocking 1 0 Reserved 1 1 Reserved inputs x 2 outputs - Non-Blocking effect effect no no effect effect Reserved 17 Zarlink Semiconductor Inc. Data Sheet Configuration ...
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... A HIGH enables the driver and a LOW disables it. Figure 5 - Connection Memory High (CMH) Bits x=Don’t care MT8986 V/C SAB3 CAB6 CAB5 MC (CM high bits) DESCRIPTION 18 Zarlink Semiconductor Inc. Data Sheet 1 0 CSTo OE ...
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... CAB4 to CAB0 (32 channel/inp. stream) CAB4 to CAB0 (32 channel/inp. stream) CAB4 to CAB0 (32 channel/inp. stream) CAB5 to CAB0 (64 channel/inp. stream) CAB5 to CAB0 (64 channel/inp. stream) CAB6 to CAB0 (128 channel/inp. stream) CAB5 to CAB0 (64 nibble/inp. stream) 19 Zarlink Semiconductor Inc. Data Sheet 1 0 CAB1 CAB0 SAB bits used to determine the source ...
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... Zarlink Semiconductor Inc. Data Sheet SAB bits used to determine the source stream for the connection SAB2, SAB1, SAB0 SAB2, SAB1, SAB0 SAB2, SAB1 SAB2 1 0 SPB1 SPB0 STi2 / STo2 STi3 / STo3 STi4 / STo4 ...
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... DESCRIPTION OFB2 OFB1 OFB0 Figure 8 - Frame Input Offset (FIO) Register 21 Zarlink Semiconductor Inc. Data Sheet Number of Clock Periods Normal Operation. No bit offsetting Reserved Reserved Reserved ...
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... STo3 STi3 • • • 4 Streams @ 4.096 Mb/s • STo7 MT8986 STo0 STi0 STo0 STo1 STi1 • 2 Streams • @ 8.192 Mb/s • • • • STo7 22 Zarlink Semiconductor Inc. Data Sheet 8 Streams @ 2.048 Mb/s OUT 8 Streams @ 2.048 Mb/s 8 Streams OUT @ 2.048 Mb/s 8 Streams OUT @ 2.048 Mb/s ...
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... Streams @2.048 Mb/s 8 Streams @4.096 Mb OUT 8 Streams @2.048 Mb/s MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 MT8986 512 x 256 23 Zarlink Semiconductor Inc. Data Sheet 4 Streams @4.096 Mb/s MT8986 4 512 x 256 OUT MT8986 4 512 x 256 4 Streams @4.096 Mb Streams @2.048 Mb/s OUT 8 8 Streams @2 ...
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... Figure 14 - Interfacing the MT8986 to the 8051 Microcontroller MT8986 LATCH MTA LE OE MT8986 Access Q LRD Q LWR Q R RES DTA 24 Zarlink Semiconductor Inc. Data Sheet RD MTA DTA OE LE MTA LATCH AD0-AD7 MT8986 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE WR ...
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... Enough time need to be provided between two CPU accesses to allow the first access to complete; i.e., to allow for an internal MT8986 reaction over the first RD/WR access. For a read operation, a minimum of 1220 ns have to be guaranteed between two successive accesses. For write, at least 800 ns has to be respected. MT8986 25 Zarlink Semiconductor Inc. Data Sheet ...
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... 100 2 0 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 -0 °C -65 +150 2 W Units Test Conditions ° Units Test Conditions ...
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... ± =5V 5%, V =0V, T =– Zarlink Semiconductor Inc. Data Sheet S1 is open circuit except when testing output levels or high impedance states switched when testing output SS levels or high impedance states. Units Test Conditions ns ns ...
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... DAA Ch. 31 STo Bit 0 Ch. 31 STi Bit 0 Figure 16 - ST-BUS Timing (CLKM bit=0) MT8986 t t CLK FRH Ch. 0 Bit Ch. 0 Bit 7 28 Zarlink Semiconductor Inc. Data Sheet Ch.0 Ch. 0 Bit 5 Bit 6 Ch. 0 Ch. 0 Bit 6 Bit 5 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V ...
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... Note: bit 0 identifies the first bit of the GCI frame WFH t t FRS FRH DAA Figure 17 - GCI Timing (CLKM bit=0) 29 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions 300 ns 150 ns ns 190 ns 190 ns 100 ns C =150 ° ...
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... C L Bit Cell Boundary (GCI) (ST-BUS SAZ * t SZA t XCD * t t OED OED Figure 19 - Output Driver Enable 30 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions KΩ*, C =150 =150 KΩ*, C =150 ...
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... FW 244 122 OED Zarlink Semiconductor Inc. Data Sheet . Units Test Conditions =150 =150 pF KΩ* ...
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... Note: For 8.192 Mb/s clock, only the positive polarity frame pulse is accepted by the MT8986 device. MT8986 Ch. 0 Ch. 0 Bit 7 Bit 6 Bit Ch. 0 Ch. 0 Bit 7 Bit Zarlink Semiconductor Inc. Data Sheet High Z Ch. 0 Bit 5 B5 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V 0.8V ...
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... MT8986 ODE STo0 * to STo9 t OED Figure 21 - Output Driver Enable for Streams at 4.096 and 8.192 Mb/s Zarlink Semiconductor Inc. 2.0V 0.8V 2.4V * 0.4V t OED 33 Data Sheet ...
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... Figure 22 - Rate Conversion Mode (DMO bit= Mb Mb/s MT8986 Ch. 0 Ch. 0 Bit 6 Bit 5 Ch. 0 Bit Ch. 0 Bit Ch. 0 Ch. 0 Bit 7 Bit 6 34 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V 2.0V 0. 2.0V High Z 0.8V 2.0V Ch. 0 Ch. 0 Bit 5 Bit 6 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V Ch. 0 Bit 6 0.8V 2.0V Ch. 0 Bit 5 0.8V ...
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... Figure 23 - Rate Conversion Mode (DMO bit= Mb Mb/s MT8986 Ch. 0 Ch. 0 Bit 6 Bit Ch. 0 Bit Ch. 0 Ch. 0 Bit 7 Bit Ch. 0 Bit 7 35 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V 2.0V 0. 2.0V High Z 0.8V 2.0V Ch. 0 Ch. 0 Bit 6 Bit 5 0.8V 2.0V 0.8V 2.0V 0.8V 2.0V Ch. 0 Bit 5 0.8V 2.0V Ch. 0 Bit 6 0.8V ...
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... MT8986 Ch. 0 Ch. 0 Bit 6 Bit 5 Ch. 0 Bit Ch. 0 Ch. 0 Bit 6 Bit Ch. 0 Bit 7 36 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V 2.0V 0. 2.0V High Z 0.8V 2.0V Ch. 0 Bit 6 0.8V 2.0V 0.8V 2.0V 0. 2.0V High Z 0. 2.0V Ch. 0 Bit 6 0.8V ...
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... SWD t 8 DHW t AKD 560 1220 300/370 730/800 125 110 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150 =150 pF,R =1 KΩ∗ ...
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... ALW ALE t t ADS ADH AD0- ADDRESS AD7 t ALRD ALWR DTA Figure 26 - Intel/National Multiplexed Bus Timing MT8986 DATA t SWD CSR CSW t DSW t DDR t AKD 38 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V 2.0V 0.8V t CSRW 2.0V 0.8V 2.0V 0.8V t DHR 2.0V 0.8V t DHW t AKH 2.0V 0.8V ...
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... DHR t 10 DSH t AKD 560 1220 300/370 730/800 125 110 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150 =150 pF KΩ∗ ...
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... DS R/W t ASW AS t ADS AD7-0 ADDRESS WR AD7-0 ADDRESS RD CS DTA Figure 27 - Motorola Multiplexed Bus Timing MT8986 t RWS t DSH ADH SWD DATA t CSS t DDR t AKD 40 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V t RWH 2.0V 0.8V 2.0V 0.8V t DHW DWS 2.0V 0.8V t DHR 2.0V DATA 0.8V 2.0V 0.8V t CSH t AKH 2.0V 0.8V ...
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... SWD t 8 DHW t AKD 560 1220 300/370 730/800 155 110 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150 =150 pF KΩ∗ ...
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... DS CS R/W A0-A6 D0-D7 READ D0-D7 WRITE DTA Figure 28 - Motorola Non-Multiplexed Bus Timing MT8986 t CSS t RWS t ADS VALID DATA t t DSW SWD VALID DATA t t DDR DHW t AKD 42 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V t CSH 2.0V 0.8V t RWH 2.0V 0.8V t ADH 2.0V 0.8V 2.0V 0.8V t DHR 2.0V 0.8V t AKH 2.0V 0.8V ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...