mt8926ap Mitel, mt8926ap Datasheet

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mt8926ap

Manufacturer Part Number
mt8926ap
Description
Iso-cmos T1 Performance Monitoring Adjunct Circuit Pmac
Manufacturer
Mitel
Datasheet

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Part Number
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Part Number:
MT8926AP
Manufacturer:
MOT
Quantity:
4 200
Features
Applications
RESET
CSTi0
CSTi1
DSTi0
DSTi1
CSTo
DSTo
ANSI T1.403 and T1.408 Performance
Monitoring and Maintenance Functions
Operates in conjunction with Mitel's T1/ESF
framer circuits (MT8976/77 and MH89760B)
D3/D4 (SF), and ESF modes of operation
One and two second timers
Supports bit-oriented and message-oriented
data transfer over the Facility Data Link (FDL)
ESF and D3/D4 Yellow Alarms, Alarm Indication
Signal and Loss of Signal Indication
Framing Error, CRC Error and Bipolar Violation
Error counters
Alarm interrupts and counter overflow interrupts
T1 line performance data collection
CSU performance monitoring
ISDN Primary Rate maintenance controller
FDLi
E8Ki
IRQ
C2i
F0i
Loopback
Interface
Payload
ST-BUS
Control
& Line
Receive BOM Register &
RAI Debounce
Transmit BOM
8 Bit CRC
Register
Counter
Timer
Figure 1 - Functional Block Diagram
Registers
Snap-
Shot
CSI
ISO-CMOS ST-BUS
Description
The MT8926 Performance Monitoring Adjunct Circuit
(PMAC) interworks with Mitel's MT8976/77 and
MH89760B to provide performance monitoring data,
alarms and T1 maintenance features.
It
maintenance requirements of ANSI T1.403 and
T1.408, and also supports Channel Service Unit
(CSU) requirements.
SEI
FSI
BSI
meets
8 Bit BPV
4 Bit SE
4 Bit FE
Counter
Counter
Counter
MT8926AE
MT8926AP
T1 Performance Monitoring
the
Ordering Information
-40°C to 85°C
Adjunct Circuit (PMAC)
performance
BPV Detector
Recovery,
AIS/LOS
Detector
B8ZS
28 Pin Plastic DIP
28 Pin PLCC
ISSUE 3
FAMILY
E8K/FDL
Loopback
Integrator
Extractor
Detector
Framer,
SE/FE
Mux
FDL
Line
monitoring
MT8926
July 1993
FDLo
E8Ko
V
V
RxA
RxB
ECLK
1SEC
DD
SS
and
4-3

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mt8926ap Summary of contents

Page 1

... Counter & Line DSTi1 Loopback Control DSTo F0i ISO-CMOS ST-BUS MT8926AE MT8926AP Description The MT8926 Performance Monitoring Adjunct Circuit (PMAC) interworks with Mitel's MT8976/77 and MH89760B to provide performance monitoring data, alarms and T1 maintenance features. It meets maintenance requirements of ANSI T1.403 and T1.408, and also supports Channel Service Unit (CSU) requirements ...

Page 2

MT8926 1 VSS ECLK 2 RxA 3 4 RxB 5 IC E8Ki 6 E8Ko 7 8 VSS 9 CSTo 10 CSTi0 11 CSTi1 F0i 12 C2i 13 VSS 14 28 PIN PLASTIC DIP Pin Description Pin # Name 1 V ...

Page 3

Pin Description (Continued) Pin # Name 13 C2i 2.048 MHz Clock Input. This input accepts a 2.048 MHz clock signal, which is used to clock ST-BUS control and data streams into and out of the PMAC. See Figures 13 and ...

Page 4

MT8926 Functional Description The MT8926 Performance Monitoring Adjunct Circuit (PMAC) is designed to enable a MT8976/77 based T1 interface to gather performance data and perform maintenance functions as per ANSI T1.403 and T1.408. Performance data collection includes CRC errors, severely ...

Page 5

XXXXXX is the message content. The PMAC will automatically append the prefix byte 11111111 to the transmit message and remove it from the receive message. It will also indicate ...

Page 6

MT8926 0-2 3 4-6 7 CSTo PS PCSW PM PCSW PCSW 1-3 4-6 Cyclic Redundancy Check-6 Error Counter PMAC Miscellaneous Status Word Bit Bit Function 7 0 7-5 Not Used 4 LLDD (001) 3 LLED (00001) 2 ...

Page 7

Bit Name 7-6 YLALR These bits (Yellow Alarm Indication and Mimic) contain information from the & MT8976/77 that is unaltered by the MT8926. See Master Status Word 1 of the MIMIC MT8976/77 data sheet. 5 ALRM Alarm. This bit will ...

Page 8

MT8926 MT8926 FDL message transfer. This 16 bit pattern must be detected in seven out of 10 codewords in order for the RAI bit of Master Status Word 1 (CSTo channel 15 bit high (see Table 3). ...

Page 9

The MT8926 PMAC can perform a payload loopback by muxing the data received on the MT8976/77’s DSTo to DSTi of the MT8976/77. This is controlled by the MT8926 Loopback Control Word (CSTi1 channel 15, see Table 4). Figure 6 illustrates ...

Page 10

MT8926 Framing Select FSel=0 101010 XXXXXX FSel=1 101010 00111X Table 7. Framing Bits which Affect the SE and FE Counters framing pattern. Refer to Table 18 for the ESF framing pattern. Table 7 illustrates ...

Page 11

Bit Name 7-0 CRC CRC Error Counter. This bit counter, which is incremented when the LSB of the MT8976/77 CRC counter toggles. The CRC error counter will wrap around after reaching terminal count (i.e., 11111111 to 00000000). ...

Page 12

MT8926 Bit Name 7-0 RxBOM Received Bit-Oriented Message. This register contains the eight least significant bits of the ESF bit oriented message codeword. The contents of this register is valid when a bit-oriented message codeword is received by the MT8926 ...

Page 13

Bit Name 7 SER SE Counter Reset. Toggling this bit from high to low will reset the severely errored framing event counter (SE counter, CSTo channel 19 bits 7-4) and event indicator (SEI bit, CSTo channel 31 bit 4). 6 ...

Page 14

MT8926 CSTo To System { 1SEC Control MT8952 FDLi CDSTo CDSTi CKi PCW FDLEn = 1 - Transmission of a Bit-oriented Message over the FDL. System Control PCW FDLEn = 0 - Transmission of an MT8952 (HDLC Controller) assembled message-oriented ...

Page 15

In slave or loop-timed operation 8KEn of the PMAC Control Word (Table 14, CSTi1 channel 11 bit 2) will be high, which will pass the signal on E8Ki through to E8Ko. In Master mode or if loop-timing is acquired from ...

Page 16

MT8926 transition of the CRCR bit (CSTi1 channel 11 bit 5, PMAC Control Word). This will ensure the CRC error counter never overflows. SLIP and SYN Interrupts The MT8976 SLIP and SYN status bits are passed to the PMAC via ...

Page 17

Applications Figure 9 illustrates a typical application of a MT8926 PMAC. T1 data is transmitted and received using a generic Line Interface Unit (LIU). The LIU passes the received data and extracted clock to both the MT8926 and MT8976. E8Ko ...

Page 18

MT8926 counter overflows and alarms. Interrupts are reset via the PMAC Control Word of the CSTi1 control stream. T1.403/408 FDL Message Transfer Overview ANSI standards T1.403 and T1.408 define an ESF mode Facility Data Link (FDL), which is used to ...

Page 19

OCTET # OCTET LABEL SAPI 2 TEI 3 CONTROL ...

Page 20

MT8926 Absolute Maximum Ratings* Parameter 1 Power Supplies with respect Voltage on any pin other than supplies 3 Current at any pin other than supplies 4 Storage Temperature 5 Continuous Power Dissipation * Exceeding these values may ...

Page 21

Received T1 Link Bit Cells 2.25V RxA, RxB 0.8V 2.25V ECLK 0.8V AC Electrical Characteristics Parameters 1 8kHz Propogation Delay 2 8kHz Setup Time 3 8kHz Input Low 4 8kHz Input High † Timing is over recommended temperature & power ...

Page 22

MT8926 AC Electrical Characteristics Parameters 1 Clock to Output Delay 2 ST-BUS Setup Time 3 ST-BUS Hold Time 4 Serial Output Delay † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and ...

Page 23

AC Electrical Characteristics Parameters 1 C2i Clock Period 2 C2i Clock Width High or Low 3 Frame Pulse Setup Time 4 Frame Pulse Width High 5 Frame Pulse Width Low † Timing is over recommended temperature & power supply voltage ...

Page 24

MT8926 Frame n CSTi0 C2i IRQ * INTA Bit. IRQ is returned to High Z by INTA=0, INTA=1 in the previous frames. This can occur in frame n later frame. ** Condition initiating interrupt Note: ...

Page 25

Appendix Control and Status Register Summary 7 6 Debounce TSPZCS B8ZS 1 Disabled 1 Disabled 1 B8ZS 0 Enabled 0 Enabled 0 Jammed Bit Master Control Word 1 (Channel 15, CSTi0) RMLOOP DGLOOP ALL 1’s 1 Enabled 1 Enabled 1 ...

Page 26

MT8926 Appendix (continued) Control and Status Register Summary UNUSED PMAC Miscellaneous Status Word (Channel 7, CSTo) Cyclic Redundancy Check-6 Error Counter (Channel 11, CSTo) YLALR MIMIC ALRM 1 Detected 1 Detected 1 Detected 0 Normal 0 Not ...

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