mt9161bs Mitel, mt9161bs Datasheet

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mt9161bs

Manufacturer Part Number
mt9161bs
Description
Iso2-cmos 5 Volt Multi-featured Codec Mfc
Manufacturer
Mitel
Datasheet

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MT9161BS
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Features
Applications
(MT9161B only)
STBd/FOod
Improved idle channel noise over MT9160
MT9161 version features a delayed framing
pulse in SSI and ST-BUS modes to facilitate
cascaded devices
Programmable -Law/A-Law Codec and Filters
Programmable ITU-T G.711/sign-magnitude
coding
Programmable transmit, receive and side-tone
gains
Fully differential interface to handset
transducers - including 300 ohm receiver driver
Flexible digital interface including ST-BUS/SSI
Serial microport or default controllerless mode
Single 5 volt supply
Low power operation
ITU-T G.714 compliant
Digital telephone sets
Cellular radio sets
Local area communications stations
CLOCKin
STB/F0i
VSSA
VBias
VSSD
Dout
VRef
VDD
Din
xxx
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xxx
xxx
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x
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x
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x
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Interface
Flexible
Digital
xxxxx
xxx
PWRST
Figure 1 - Functional Block Diagram
Channels
ST-BUS
C & D
Timing
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IC
FILTER/CODEC GAIN
ENCODER
DECODER
CS
x x
x x
Description
The
incorporates a built-in Filter/Codec, gain control and
programmable sidetone path as well as on-chip
anti-alias filters, reference voltage and bias source.
The device supports both ITU-T and sign-magnitude
A-Law and -Law requirements.
Complete telephony interfaces are provided for
connection to handset transducers. Internal register
access is provided through a serial microport
compatible
micro-controllers.
controllerless operation utilizing the default register
conditions.
The
ISO
consumption and high reliability.
DS5145
x x
x x
x x
x
-7dB
5 Volt Multi-Featured Codec (MFC)
7dB
MT9161BE
MT9160BE
MT9161BS
MT9160BS
MT9161BN
MT9160BN
2
-CMOS
DATA1
MT9160B/61B
MT9160B/61B
Serial Microport
x
x x
ISO
xxx
xxx
2
DATA2
with
-CMOS
technology
x x
x x
Transducer
Ordering Information
Interface
-40 C to +85 C
The
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SCLK
various
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x x
x x
24 Pin Plastic DIP(600 mil)
24 Pin Plastic DIP(600 mil)
24 Pin SOIC
20 Pin SOIC
24 Pin SSOP
20 Pin SSOP
5V
is
ISSUE 3
Advance Information
MT9160B/61B
device
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fabricated
ensuring
Multi-featured
xxxxxxx
industry
also
x x
x x
x x
x x
x
x x
x x
x
x x
x x
x x
x x
x
x x
x x
x x
x x
low
in
M -
M +
HSPKR +
HSPKR -
A/ /IRQ
standard
supports
March 1999
Codec
Mitel's
power
79

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mt9161bs Summary of contents

Page 1

... STBd/FOod x x (MT9161B only ISO 5 Volt Multi-Featured Codec (MFC) DS5145 MT9161BE MT9160BE MT9161BS MT9160BS MT9161BN MT9160BN Description The MT9160B/61B incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias filters, reference voltage and bias source. The device supports both ITU-T and sign-magnitude A-Law and -Law requirements ...

Page 2

MT9160B/61B MT9160BS/BN 1 VBias VRef PWRST VSSA HSPKR + 5 A/ /IRQ 16 HSPKR - VSSD 6 VDD CLOCKin 8 SCLK 13 STB/F0i DATA1 ...

Page 3

Advance Information Pin Description (continued) Pin # Pin # Name 20 Pin 24 Pin 13 15 STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive ...

Page 4

MT9160B/61B In the event of PWRST, the MT9160B/61B defaults such that the side-tone path is off, all programmable gains are set to 0dB and ITU-T Further, the digital port is set to SSI mode operation at 2048 kb/s and the ...

Page 5

Advance Information Filter/Codec and Transducer Interface Serial Port Receive Decoder Filter Gain PCM 2.05dB steps) in PCM Transmit Filter Transmit Filter Encoder Gain Gain -2.05dB ...

Page 6

... Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire 84 Flexible Digital Interface A serial link is required to transport data between the MT9160B/61B and an external digital transmission device. The MT9160B/61B utilizes the ST-BUS architecture defined by Mitel Semiconductor but also DATA INPUT/OUTPUT ...

Page 7

... Dout and Din respectively, a synchronous clock input signal CLOCKin (C4i), and a framing pulse input (F0i). These signals are direct connections to the corresponding pins of Mitel basic rate devices. The CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS operation. The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s bandwidth ...

Page 8

MT9160B/61B DEN: When 1, ST-BUS D-channel data ( bits/frame depending on the state of the D8 bit) is shifted into/ out of the D-channel (READ/WRITE) register. When 0, the receive D-channel data (READ) is still shifted into the ...

Page 9

Advance Information IRQ FP n-3 n-2 DSTo/ DSTi Di-bit Group I II Receive D-Channel No preset value * note that frame n+4 is equivalent to frame n of the next cycle. FP C4i C2 DSTo/ D0 ...

Page 10

MT9160B/61B SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), a framing strobe input (STB) and the MT9161B provides a delayed framing strobe output (STBd). The ...

Page 11

MT9160B/61B Register Summary Address Bit 7 Bit 6 00 RxINC RxFG PDFDI PDDR 04 CEN DEN 07y - - Table 2 - ...

Page 12

Advance Information Gain Control Register Side-tone Gain Setting (dB) (default) OFF -9.96 -6.64 -3.32 0 3.32 6.64 9.96 STG = Side-tone Gain bit n n Path Control - - - ...

Page 13

MT9160B/61B Control Register 1 PDFDI PDDR Rst PDFDI When high, the FDI PLA and the Filter/Codec are powered down. When low, the FDI is active (default). PDDR When high, the ear driver and Filter/Codec are powered down. ...

Page 14

Advance Information C-Channel Register Micro-port access to the ST-BUS C-Channel information read and write D-Channel Register D7-D0 Data written to this register will be transmitted every frame, in ...

Page 15

MT9160B/61B Applications Figure 9 shows an application in a digital phone set. Various configurations of pair gain drops are depicted in Figures 12a and 12b using the MT9125 and MT9126, respectively. 330 + ...

Page 16

Advance Information VBias x x 0.1 F xxx 0.1 F 0.1 F xxx 100K xx +5V A/ /IRQ INTEL CS MCS-51 or SCLK MOTOROLA SPI DATA1 Micro- DATA2 ...

Page 17

MT9160B/61B Absolute Maximum Ratings Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin (transducers excluded) 4 Storage Temperature 5 Power Dissipation (package) † Exceeding these values may cause permanent damage. Functional operation under ...

Page 18

Advance Information DC Electrical Characteristics Characteristics 1 Input HIGH Voltage CMOS inputs 2 Input LOW Voltage CMOS inputs 3 VBias Voltage Output 4 V Output Voltage Ref 5 Input Leakage Current 6 Positive Going Threshold Voltage (PWRST only) Negative Going ...

Page 19

MT9160B/61B † AC Characteristics for A/D (Transmit) Path - 3.14dB =1.843V for A-Law, at the Codec (V rms Characteristics 1 Analog input equivalent to overload decision 2 Absolute half-channel gain M to Dout Tolerance at all other transmit filter settings ...

Page 20

Advance Information † AC Characteristics for D/A (Receive) Path 3.14dB =1.843V for A-Law, at the Codec. (V rms Characteristics 1 Analog output at the Codec full scale 2 Absolute half-channel gain. Din to HSPKR Tolerance at all other receive filter ...

Page 21

MT9160B/61B AC Electrical Characteristics Characteristics 1 Absolute path gain gain adjust = 0dB 2 Tolerance of other side-tone settings (-9.96 to 9.96 dB) relative to output at 0dB setting † AC Electrical Characteristics are over recommended temperature range & recommended ...

Page 22

Advance Information AC Electrical Characteristics Characteristics 1 C4i Clock Period 2 C4i Clock High period 3 C4i Clock Low period 4 C4i Clock Transition Time 5 F0i Frame Pulse Setup Time 6 F0i Frame Pulse Hold Time 7 Delayed Frame ...

Page 23

MT9160B/61B AC Electrical Characteristics Characteristics 1 BCL Clock Period 2 BCL Pulse Width High 3 BCL Pulse Width Low 4 BCL Rise/Fall Time 5 Strobe Pulse Width 6 Delayed Strobe Pulse Width 7 Strobe setup time before BCL falling 8 ...

Page 24

Advance Information t t BCLH t R CLOCKin 70% (BCL) 30% t DIS 70% Din 30% t DOZL 70% Dout 30% t DOZH 70% STB 30% 70% STBd 30% Figure 12 - SSI Synchronous Timing Diagram AC Electrical Characteristics Characteristics ...

Page 25

MT9160B/61B 70% STB 30% t dda2 t dha1 t dda1 70% Dout Bit 1 30% T DATA1 70% Din D1 30 DATA Figure 13 - SSI Asynchronous Timing Diagram AC Electrical Characteristics Characteristics 1 ...

Page 26

Advance Information 2. 0. xxx IDS x xxxx IDH xxxx t CH xxx xxx xxx x ...

Page 27

x xxx x x xxx xxx x xxx x x xxx x x xxx xxx xxx ...

Page 28

Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...

Page 29

Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...

Page 30

... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...

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