mt9123apr1 Zarlink Semiconductor, mt9123apr1 Datasheet - Page 19

• Manufacturer Part Number: mt9123apr1
• Description: Dual Voice Echo Canceller Itu-t G165 Compliant
• Manufacturer: Zarlink Semiconductor

Register Summary
MuteR
MuteS
HPFDis
NBDis
NLPDis
Note: Bits marked as “0” are reserved bits and should be written as indicated.
Extended-
AdaptDis
Bypass
PAD
BBM
INJDis
Reset
Note: Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Delay
Echo Canceller A, Control Register 1
CRA1
Echo Canceller B, Control Register 1
CRB1
Echo Canceller A, Control Register 2
Echo Canceller B, Control Register 2
CR2
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.
When high, the non-linear processor is disabled.
When low, the offset nulling filters are active and will remove DC offsets on PCM input signals.
When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.
When low, the non-linear processors function normally. Useful for G.165 conformance testing.
When high, Echo Cancellers A and B are internally cascaded into one 128ms echo canceller.
When high, echo canceller adaptation is disabled.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout.
When high, 12 dB of attenuation is inserted into the Rin to Rout path.
When high the Back to Back configuration is enabled.
When high, the noise injection process is disabled. When low noise injection is enabled.
When high, the power-up initialization is executed presetting all register bits including this bit.
When low, Echo Cancellers A and B operate independently.
Do not enable both Extended-Delay and BBM configurations at the same time.
When low, the echo canceller dynamically adapts to the echo path characteristics.
When low, output data on both Sout and Rout is a function of the echo canceller algorithm.
When low the Rin to Rout path gain is 0 dB.
When low the Normal configuration is enabled. Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers to the same logic value to avoid conflict.
Reset
Reset
7
7
0
7
INJDis
INJDis
6
6
0
6
NLPDis
BBM
BBM
5
5
5
PAD
PAD
4
4
0
4
Zarlink Semiconductor Inc.
Bypass
Bypass
NBDis
3
3
3
MT9123
AdaptDis
AdaptDis
HPFDis MuteS
19
2
2
2
1
1
1
1
0
Extended
Delay
MuteR
ADDRESS = 00h WRITE/READ VERIFY
ADDRESS = 01h WRITE/READ VERIFY
ADDRESS = 20h WRITE/READ VERIFY
ADDRESS = 21h WRITE/READ VERIFY
0
0
0
0
Power Reset Value
Power Reset Value
Power Reset Value
0000 0000
0000 0010
0000 0000
Data Sheet