m21330 Mindspeed Technologies, m21330 Datasheet

no-image

m21330

Manufacturer Part Number
m21330
Description
4.25 Gbps Quad-channel Cable Driver And Adaptive Equalizer With 4x4 Crosspoint Switch
Manufacturer
Mindspeed Technologies
Datasheet
M21330
4.25 Gbps Quad-Channel Cable Driver and Adaptive Equalizer
with 4x4 Crosspoint Switch
The M21330 is a quad channel device designed to enable the transmission of multi gigabit serial data through the
most challenging environments. The device features four independent adaptive equalizers that automatically
equalize data at rates up to 4.25 Gbps. Full register control of the M21330 is provided through an I
software control interface. The M21330 can also self-configure from an external EEPROM without the need for a
host processor. For compatibility with PCI-Express and S-ATA/SAS systems, the M21330 is designed with an
electrical idle pass-through function to drive the differential output to the common mode level during OOB signaling.
Boundary scan is provided for high-speed input and output pins through a JTAG port, and the device is available in
a 6x6 mm, 40-pin QFN package.
Features
• Adaptive equalization for up to 20m of 24 AWG cable at
• Supports electrical idle signaling for PCIe and OOB signaling for
• Low power dissipation: 145 mW per channel, 580 mW total
• Up to 35 dB of input equalization and 6 dB of output de-
• Software and EEPROM programmable
• 6x6 mm, 40-pin QFN package
• Extended operating case temperature range (-20
• Integrated 4x4 Crosspoint Switch Matrix
21330-DSH-001-B
4.25 Gbps
S-ATA/SAS
power at 1.2V
emphasis
programmable DeEmphasis
Driver and Equalizer
M
Output drivers with
21330
Mindspeed Technologies
°
Up to 20m of 24 AWG
C to 85
Cable at 4.25 Gbps
Typical Application Diagram
°
C)
Applications
XAUI
S-ATA/SAS
PCIe
Fibre
Channel
Infiniband
SDI Video
Closed eye after
long cable
®
1.0625 Gbps
3.125 Gbps
270 Mbps
1.5 Gbps
2.5 Gbps
2.5 Gbps
Adaptive Input Equalizers
Driver and Equalizer
M
21330
1.485/1.001 Gbps
2.125 Gbps
1.485 Gbps
3.0 Gbps
2
C compatible
2.97/1.001 Gbps
Open eye after
equalization
4.25 Gbps
2.97 Gbps
August 2009

Related parts for m21330

m21330 Summary of contents

Page 1

... Gbps Quad-Channel Cable Driver and Adaptive Equalizer with 4x4 Crosspoint Switch The M21330 is a quad channel device designed to enable the transmission of multi gigabit serial data through the most challenging environments. The device features four independent adaptive equalizers that automatically equalize data at rates up to 4.25 Gbps. Full register control of the M21330 is provided through an I software control interface ...

Page 2

... DINP1, the correct label for pin 19 is DINN2). Added thermal resistance parameters to Inserted comments in Section 5.1 be powered-up and stable before powering-up the M21330 in MIC mode for robust operation. January 2009 Initial release. M21330 Marking Diagram 21330G14 ...

Page 3

... Case Temperature C θ Junction to ambient thermal resistance (no airflow) JA θ Junction to ambient thermal resistance (2.5 m/s airflow) JA θ Junction to case thermal resistance JC 21330-DSH-001-B Parameter Minimum 1.14 1.14 2.37 –20 — — — ® Mindspeed Technologies Minimum Maximum — 2.1 — 1.5 — 3.6 –65 150 — 2000 — 500 Typical Maximum 1.2, 1.8 1.89 1.2 1.26 2.5, 3.3 3.47 — ...

Page 4

... Note Minimum — — — — — — AVDDIO - 0.05 1,2,3 — — — 0.85 x DVDDIO — 0.25 x DVDDIO — ® Mindspeed Technologies Electrical Characteristics Typical Maximum — — 130 150 — 440 530 — 2 — — 580 735 — 765 955 C case temperature, 800 ° ...

Page 5

... Two-wire serial interface can drive 500 pF @ 100 kHz and 400 kHz, 100 pF at 3.4 MHz. 6. Measured using a CID pattern with a minimum CID length of 10 bits. 21330-DSH-001-B Note Minimum 5 0.85 x DVDDIO 5 Figure 2-5 for typical output swing levels for each setting. ® Mindspeed Technologies Electrical Characteristics Typical Maximum — — — — 0.15 x DVDDIO Unit V V ...

Page 6

... Eye Diagram at 3.125 Gbps Figure 2-2. Eye Diagram after 15m of 24 AWG Cable at 4.25 Gbps 21330-DSH-001-B Characteristics Figure 2-3. Figure 2-4. ® Mindspeed Technologies C case temperature, 800 mV ° test pattern at 4.25 Gbps Eye Diagram at 4.25 Gbps Eye Diagram after Equalizing 15m 24 AWG Cable at 4.25 Gbps Ω ...

Page 7

... Figure 2- 10m ® Mindspeed Technologies Typical Performance Characteristics Output Waveform With COMWAKE OOB Signal COMWAKE Jitter vs. Data Rate as a Function of 24 AWG Cable Length DJ @ 15m 20m ...

Page 8

... Amplitude as a Function of Data Rate (After Equalizing 10m 24 AWG Cable 1.5 G bps bps DJ @ 4.25 G bps litu Error Detector/ M21330 Digital Evaluation Communications Module Analyzer 8 ...

Page 9

... Package Description The M21330 is assembled mm, 40-pin QFN package. The package paddle is used to provide the device ground connection as well as a thermal path. Figure 3-1. Package Outline Drawing A D D 0.60 DIA TOP VIEW 2X (DATUM (L) ...

Page 10

... DOUTN0 3 DOUTP0 MF1 4 MF2 5 ADDR0 6 7 ADDR1 DINP0 8 9 DINN0 TDI 21330-DSH-001-B Package Description and Package Outline Drawing M21330 6x6 mm 40-pin QFN ® Mindspeed Technologies 30 AVDDIO DOUTP3 29 DOUTN3 28 27 xALARM 26 RSVD 25 RSVD 24 MF0 DINN3 23 DINP3 22 ...

Page 11

... Pins 25 and 26 are reserved for use as REFCLK connections on the M21330. MSPD recommends that a REFCLK circuit is designed into the system PCB if feasible to enable future use of the M21340 on the same PCB if necessary. ...

Page 12

... Control Registers Map and Table 4-1. M21330 Register Summary Table Register D7 Address D6 Name (MSB) 00h devctrl0 01h devctrl1 standby 02h eqconfig eqen 03h inctrl in3pwr 04h maneqlvl10 05h maneqlvl32 06h outctrl0 outlvl 07h outctrl1 outlvl 08h outctrl2 outlvl 09h outctrl3 outlvl 0Ah ...

Page 13

... Table 4-1. M21330 Register Summary Table Register D7 Address D6 Name (MSB) 87h alarm_int FCh MIC Checksum * See register description for details on contents of the chip revision register (address 82h). Address 00h—Device Control 0 Bits Type Default [7:1] RSVD 0000000 MSPD 0 R/W 0 bpen0 Address 01h—Device Control 1 ...

Page 14

... Minimum equalization 1110: Low equalization .... .... 1000: Medium equalization 0000: Medium equalization .... 0110: High equalization 0111: Maximum equalization Input equalization is programmed using 2's complement encoding, with 111 being the lowest eq setting and 0111 being the highest eq setting. ® Mindspeed Technologies Description Description 14 ...

Page 15

... Maximum Output Swing Reserved, set to 0 Controls output de-emphasis. 00: Output de-emphasis disabled. 01: Approximately 2 dB de-emphasis. 10: Approximately 4 dB de-emphasis. 11: Approximately 6 dB de-emphasis. 0: Nominal time constant for output de-emphasis. 1: High time constant for output de-emphasis. Reserved, set to 0. ® Mindspeed Technologies Description Description 15 ...

Page 16

... Declare LOS after approx 5us of no input data. 1: Declare LOS after approx 1us of no input data. Reserved, set to 0000. Label Identifies the number of M21330 devices on the bus for Memory Interface Control mode. 00000: No additional M21330 devices on serial buss ... 11010: Maximum number(26) of additional M21330 devices on serial buss Reserved, set to 000. ® ...

Page 17

... SDI video to enable best performance with pathological data patterns) Reserved, set to 0000. ® Mindspeed Technologies Description Description Description 17 ...

Page 18

... AAh followed by a second write of 00h) Label Device identification register. Label Device revision register. M21330G-14 = 05h Label 0: No alarm for input channel 3. 1: LOS alarm for input channel alarm for input channel 2. 1: LOS alarm for input channel 2. ...

Page 19

... Reserved, set to 100. Label After an EEPROM download, this register contains the checksum calculated value. If this value is not equal to 2Eh after an MIC download, there was either an issue with the download or the checksum seed value in register 1Fh is not correct. ® Mindspeed Technologies Description Description 19 ...

Page 20

... Functional Description The M21330 is a quad channel device with adaptive input equalization, programmable output de-emphasis, and an embedded 4x4 crosspoint switch matrix. Details on various functionality and features are described in the following sections. Figure 5-1. Functional Block Diagram DIN0P Input Buffer with Adaptive Equalization ...

Page 21

... Input and Output Buffers The input buffers in the M21330 are designed to work with AC coupled input signals, and support operation with a wide range of AC coupling capacitor values. Applications that use PRBS and/or 8b/10b encoded data will typically use AC coupling capacitors with a value of 0.1 µF. SDI video applications will typically use AC coupling capacitors with a value of 4.7 µ ...

Page 22

... EI circuit is enabled to allow the device to detect data bursts quickly after electrical idle periods that last longer than approximately 5 us. The EI feature is enabled/disabled through register address 01h, and is disabled by default. Note: If the M21330 is used in a PCIe application that requires support of the L0s power management state, contact your Mindspeed representative for details on using the device in this application. ...

Page 23

... Squelch To avoid random chattering of the output due to noise when there is no signal present at the inputs, the M21330 includes a squelch feature to automatically inhibit the output when there is a LOS alarm. This feature can be disabled if desired, and there is an option to inhibit to either logic H, logic L, or the EI common mode level on squelch. In addition to the automatic squelch feature, a manual squelch can be forced using register 0Bh. LOS should be set to " ...

Page 24

... Refer to M21330. To access the registers SDA is used for data transfer and is mapped to MF1 when the M21330 is configured for SIC operation. SCL is used for the clock signal and is mapped to the pin MF2 when the M21330 is configured for SIC operation. The two-wire device address is determined by the status of the pins ADDR[2:0] ...

Page 25

... The two wire programming interface is designed to drive 500 pF at 100 and 400 kHz, and 100 pF at 3.4 MHz operation. During a write operation, data is latched into the M21330 registers on the rising edge of SCL during the acknowledge phase (ACK) of communication. Refer to the I is applicable to the two-wire programming interface. ...

Page 26

... Register address 0Ch is used to identify the number of M21330 that will be self configured by the quasi master in MIC mode. When multiple M21330 devices are self configured in an array, the quasi master M21330 device will copy its register contents into other devices in the array sequentially using a 400 kHz interface buss ...

Page 27

... Newport Beach, CA 92660 © 2007-2009 Mindspeed Technologies ® , Inc. All rights reserved. Information in this document is provided in connection with Mindspeed Technologies ® ("Mindspeed ® ") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever ...

Related keywords