zl30130 Zarlink Semiconductor, zl30130 Datasheet
zl30130
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zl30130 Summary of contents
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... T4 DPLL1 ref /sync hold 2 JTAG I C/SPI Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30130 Short Form Data Sheet February 2008 Ordering Information 100 Pin CABGA Trays 100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper p1_clk0 Synthesizer ...
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... O APLL Output Clock 1 (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet clock rates up to 125 MHz. The default frequency for this output is 19.44 MHz. ZL30130 Description . dd dd. Leave open when not in use. ...
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... A logic low disables hitless reference switching and re-aligns DPLL1’s output phase to the phase of the selected reference input. This feature can also be controlled through software registers. This pin is internally pulled up to Vdd. ZL30130 Description 6 Zarlink Semiconductor Inc. ...
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... VDD i2c_en Interface Enable (LVCMOS). If set high, the I u low, the SPI interface is enabled. Internally pull-up to Vdd. ZL30130 Description 2 C interface interface. 7 Zarlink Semiconductor Inc. Short Form Data Sheet ...
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... Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. Miscellaneous J6 IC Internal Connection. Connect to ground Internal Connection. Leave unconnected Connection. Leave unconnected ZL30130 Description 8 Zarlink Semiconductor Inc. Short Form Data Sheet . If this pin is not used DD ...
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... Analog Ground. 0 Volts Input, Internally pulled down Input, Internally pulled Output A - Analog P - Power G - Ground ZL30130 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Short Form Data Sheet I - Input ...
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... F si sdh G so int_b IC H dpll1_lock AV AV CORE SS J dpll1_hold i2c_en tms K diff0_en tdi tck corner is identified by metallized markings. ZL30130 ref7 AV apll_filter ref5 sync8/ filter_ref0 AV CORE ext_fb_fp ref6 ref8/ filter_ref1 AV SS ext_fb_clk ...
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... High Level Overview The ZL30130 SONET/SDH/GbE Stratum 2/3E/3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a central timing card include: • Input reference monitoring for both frequency accuracy and phase irregularities • ...
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... Alternatively, the ZL30130 could be used in systems that were not designed with central timing cards in mind. In this case, the ZL30130 provides all of the features required to meet both the timing card and the line card functions in one package. This application is shown in Figure 3. DPLL1 recovers the reference clock from the backplane and filters wander ...
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... Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...