zl30145 Zarlink Semiconductor, zl30145 Datasheet

zl30145

Manufacturer Part Number

zl30145

Description

Synce 10 Gbe Sonet/sdh Rate Conversion And Jitter Attenuator Pll

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL30145.pdf (4 pages)

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zl30145GGG2

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Features

•

Can be used in systems to support the

requirements of ITU-T G.8262 for synchronous

Ethernet Equipment slave Clocks (EEC option 1

and 2)

Meets jitter generation requirements of Telcordia

GR-253-CORE for OC-192, OC-48, OC-12 and

OC-3 rates

Meets jitter generation requirements of ITU-T G.813

for STM-64, STM-16, STM-4 and STM-1 rates

Synchronizes to standard telecom or Ethernet clock

and provides jitter filtered output clock for

SONET/SDH and Synchronous Ethernet line cards

Synchronizes to telecom reference clocks (2 kHz,

N*8 kHz up to 77.76 MHz, 155.52 MHz) or to

Ethernet reference clocks (25 MHz, 50 MHz,

62.5 MHz, 125 MHz)

Generates standard SONET/SDH clock rates (e.g.,

19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,

622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,

50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for

synchronizing Ethernet PHYs

Selectable loop bandwidth of 14 Hz, 28 Hz, or

890 Hz

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ref

Figure 1 - Simplified Functional Block Diagram

lock

osci

Zarlink Semiconductor Inc.

hold

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DPLL

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Conversion and Jitter Attenuator PLL

•

Applications

•

Configurable through a serial interface (SPI or I

DPLL can be configured to provide synchronous or

asynchronous clock outputs

Supports IEEE 1149.1 JTAG Boundary Scan

ITU-T G.8262 Line Cards which support 1 GbE

and 10 GbE interfaces

SONET line cards up to OC-192

SDH line cards up to STM-64

SyncE (10 GbE) SONET/SDH Rate

ZL30145GGG

ZL30145GGG2

C/SPI

SONET/SDH/

Ethernet

APLL

*Pb Free Tin/Silver/Copper

JTAG

Ordering Information

-40

64 Pin CABGA

64 Pin CABGA*

C to +85

Short Form Data Sheet

diff

apll_clk

ZL30145

Trays

February 2009

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