mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 126

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

17.1.4
Tables 80 to 95 describe the bit functions of each of the Master Status Registers in the MT9072. Each register is
repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2 with Y=2... and
Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB) A
power up in the inactive state until the event happens.
15-14
Bit
13
12
10
11
9
8
7
6
5
4
3
MFSYNC Multiframe Synchronization. Indicates the Multiframe Synchronization status (1 - loss; 0
Master Status Registers(Y10-Y18)Bit Functions
TFSYNC Terminal Frame Synchronization. Indicates the Terminal Frame Synchronization status (1
SECYEL Secondary D4 Yellow Alarm. This bit is set if 2 consecutive’1’s are received in the S-bit
D4YALM D4 Yellow Alarm. This bit is set if bit position 2 of virtually every DS0 channel is a zero for a
ESFYEL
D4Y48
Name
LLED
LOS
PDV
AIS
SE
#
not used
- loss; 0 - acquired). For ESF links terminal frame synchronization and multiframe
synchronization are synonymous.
This bit is also used for indicating T1DM sync gain or loss.
-acquired). For ESF Mode multiframe synchronization and terminal frame synchronization
are synonymous. MFSYNC is relevant in all T1 Modes.
Severely Errored Frame. This bit toggles when 2 of the last 6 received framing bits are in
error. The framing bits monitored are the ESF framing bits for ESF links, a combination of Ft
and Fs bits for D4 links (See Framing Mode Selection Word Y00) and T1DM Mode.
Digital Loss of Signal. This bit goes high after the detection of 192 or 32 consecutive zeros
dependent on the setting of L32Z bit. It returns low when the incoming pulse density exceeds
12.5%.
period of 600 milliseconds. The alarm is tolerant of errors by permitting up to 16 ones in a 48
millisecond integration period. The alarm clears in 200 milliseconds after being removed
from the line. The alarm will also clear if four 48 msec intervals are detected with more than
16 ones in bit position 2.
D4 Yellow Alarm - 48 Millisecond Sample. This bit is set if bit position 2 of virtually every
DS0 channel is a zero for a period of 48 milliseconds. The alarm is tolerant of errors by
permitting up to 16 ones in the integration period. This bit is updated every 48 milliseconds.
position of the 12th frame of the D4 superframe.
ESF Yellow Alarm. This bit is set if the ESF yellow alarm 0000000011111111 is received in
eight or more codewords out of ten in the Bit oriented message location which are the FDL
bits.
AIS Alarm. This bit is set if less than 5 zeros are received in a 3 millisecond window. The
AIS bit is set to ahigh after power up.
Pulse Density Violation. This bit toggles if the receive data fails to meet ones density
requirements. It will toggle upon detection of 16 consecutive zeros on the line data, or if
there are fewer than N ones in a window of 8(N+1) bits - where N = 1 to 23.
Line Loopback Enable Detect. This bit will be set when a framed or unframed repeating
pattern of 00001 has been detected during a 48 millisecond interval. Up to fifteen errors are
permitted per integration period. Note that the code detected is dependent on Receive
Loopback Activate Code Match(Y0F).
Table 79 - Synchronization and Alarm Status Word(Y10) (T1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
126
11
A
10
A
9
A
8
). All status bits will
Data Sheet