mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 128

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-14
13-11
7-3
2-0
Bit
10
9
8
RxBC2 - 0 Receive Bit Count. A three bit counter that indicates the number of ST-BUS bit times
RxTS4 - 0 Receive Timeslot. A five bit counter that indicates the number of timeslots between the
RxSLIP
RxFRM
RSLPD
Name
PI2-0
#
not used.
Phase Indicator Bits (PI2 to PI0). These bits make up 3 least significant bits of a 12 bit
word which indicate the delay through the receive slip buffer. The delay through the slip
buffer in 2.048 Mhz bit cells is ( 512 - Phase Indicator bits). The delay to DSTo from the
write into the slip buffer is ( 512 - Phase Indicator bits) + 16 bits. These bits are updated
when the slip buffer write address is 0. These 3 bits will reflect the 1/2,1/4 and 1/8
fractions of the Phase Indicator Bits.
Receive Slip Direction. If one, indicates that the last received frame slip resulted in a
repeated frame, i.e., the system clock (C4b) is faster than network clock (EXCLi). If zero,
indicates that the last received frame slip resulted in a lost frame, i.e., system clock slower
than network clock. Updated on an RSLIP occurrence basis.
Receive Slip. A change of state (i.e., 1-to-0 one 0-to-1) indicates that a receive controlled
frame slip has occured.
Receive Frame. The most significant bit of the phase status word. If one, the delay
through the receive elastic buffer is greater than one frame in length; if zero, the delay
through the receive elastic buffer is less than one frame in length.
receive elastic buffer internal write frame boundary and the ST-BUS read frame boundary.
The count is updated every 250 uS.
there are between the receive elastic buffer internal write frame boundary and the ST-BUS
read frame boundary. The count is updated every 250 uS.
Table 82 - Receive Slip Buffer Status Word(Y13) (T1)
Zarlink Semiconductor Inc.
MT9072
128
Functional Description
Data Sheet