mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 133

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-9
Bit
8
7
6
5
4
3
2
1
0
TxunderL
EOPDL
EOPRL
TEOPL
RXOvfl
TXFLL
Name
RxffL
GAL
FAL
#
not used.
Go Ahead received Latch. Indicates a go-ahead pattern (01111111) was detected by the
HDLC receiver. This bit is cleared after a read of Y23 or Y33.
End of Packet Data Latch. This bit is set when an end of packet (EOP) byte was written
into the RX FIFO by the HDLC receiver. This can be in the form of a flag, an abort
sequence or as an invalid packet. This bit is cleared after a read of Y23 or Y33.
Transmit End of Packet Latch. This bit is set when the transmitter has finished sending
the closing flag of a packet or after a packet has been aborted. This bit is cleared after a
read of Y23 or Y33.
End of Packet received latch. This bit is set when the byte about to be read from the RX
FIFO is the last byte of the packet. It is also set if the Rx FIFO is read and there is no data
in it. This bit is cleared after a read of Y23 or Y33.
Transmit Fifo Low Latch. This bit is set when the Tx FIFO is emptied below the 16 byte
low threshold level. This bit is cleared after a read of Y23 or Y33.
Framer Abort Latch. This bit (FA) is set when a frame abort is received during packet
reception. It must be received after a minimum number of bits have been received (26)
otherwise it is ignored.This bit is cleared after a read of Y23 or Y33.
Txunder Latch. This bit is set for a TX FIFO underrun indication. If high it indicates that a
read by the transmitter was attempted on an empty Tx FIFO. This bit is cleared after a read
of Y23 or Y33.
Receive Fifo Full Latch. This bit is set when the Rx FIFO is filled above the 16 byte full
threshold level. This bit is reset after a read.This bit is cleared after a read of Y23 or Y33.
Receive Overflow Latch. Indicates that the 32 byte RX FIFO overflowed (i.e. an attempt to
write to a 32byte full RX FIFO). The HDLC will always disable the receiver once the receive
overflow has been detected. The receiver will be re-enabled upon detection of the next flag,
but will overflow again unless the RX FIFO is read. This bit is reset after a read.This bit is
cleared after a read of Y23 or Y33.
Table 95 - HDLC Status Latch(Y23) (T1)
Zarlink Semiconductor Inc.
MT9072
133
Functional Description
Data Sheet