mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 143

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15 - 4
Bit
3
2
1
0
Name
RA(n) Receive Signaling Bits A for Channel n. Where signaling is enabled, these bits are received in
RB(n) Receive Signaling Bits B for Channel n. Where signaling is enabled, these bits are received in
RC(n) Receive Signaling Bits C for Channel n. Where signaling is enabled, these bits are transmitted
RD(n) Receive Signaling Bits D for Channel n. Where signaling is enabled, these bits are transmitted
#
not used.
bit position 8 of the 6th DS1 frame (within the 12 frame superframe structure for D4 superframes
and the 24 frame structure for ESF superframes).This data can be overwritten by the microport
for trunk conditioning applications.
bit position 8 of the 12th DS1 frame (within the 12 frame superframe structure for D4
superframes and the 24 frame structure for ESF superframes).This data can be overwritten by
the microport for trunk conditioning applications.
in bit position 8 of the 18th DS1 frame within the 24 frame structure for ESF superframes. In D4
mode these bits are unused.This data can be overwritten by the microport for trunk conditioning
applications
in bit position 8 of the 24th DS1 frame within the 24 frame structure for ESF superframes. In D4
mode these bits are unused.This data is obtained from the CSTi interface but can be overwritten
via the Micro port for trunk conditioning applications.This data can be overwritten by the
microport for trunck conditioning applications.
Table 110 - Per Channel Receive Signaling Y70-Y87 (T1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
143
Data Sheet