mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 149

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

17.1.10
The Global Control and Status Registers are common to the T1 and E1 operation. The global registers are
accessed by address hex 9xx ( A
13-5
3-1
15-8
Bit
15
14
7-0
Bit
4
0
STBUS
(00000000)
Name
RSTC
T1E0
CK1
TxSD7-0
Global Control and Status Registers (900 - 91F) Bit Functions
(1)
(0)
(0)
(0)
#
#
Name
#
T1E0. This bit determines if the chip will operate in T1 or E1 mode for all 8 framers. If the value
of this bit is changed the chip is reset in E1 or T1 default register mode. If the bit is set to 1, all
the framer register values are set to T1 defaults. For a setting of 0 the register values are set to
E1 defaults. This action takes approximately 34 1.5444 clock cycles. Hence any writes to
registers should be done on the next 125 usec frame after setting or clearing this bit.
ST-BUS Enable. If zero, ST-BUS timing is enabled. If one, GCI timing is enabled (only
available for 2.048 Mb/s mode). See Figures 24-31.
not used.
Clock Rate. This clock select bit determines the system clock at the CKi pin and the receive
frame pulse at the FPi pin as follows (See Figures 24 to 31):
CK1
0
1
not used.
Common Reset. When this bit is changed from zero to one, all eight framers will reset to their
default T1 mode. This software reset has the same effect as the RESET pin. See the Reset
Operation section for the default settings.
not used.
Transmit Set Delay Bits 7 - 0. Writing to this register forces a one time setting of the delay
through the transmit slip buffer. The binary value written to the Transmit Set Delay Bits
defines the delay between the write of the Transmit ST-BUS Channel containing DS1
timeslot 1 (first timeslot) and its read from the slip buffer.
If the value written to the Transmit Set Delay Bits is 00H to BFH then the delay can be
calculated as: (Value) / (1.544 x 10
If the value written to the Transmit Set Delay Bits is C0H to FFH then the delay can be
calculated as: (255 - value) / (2.048 x 10
After a reset there will be an immediate transmit slip and the subsequent delay through the
transmit slip buffer will be one frame.
Table 119 - Global Control0 Register (R/W Address 900) (T1)
11
Table 118 - TX Set Delay Bits (YF7) (T1)
and A
Clock
4.096 MHz
16.384 MHz
8
being high and A
Zarlink Semiconductor Inc.
MT9072
Functional Description
149
Functional Description
Frame Pulse
6
2.048 Mb/s
8.192 Mb/s
) seconds.
10
6
and A
) seconds.
9
being low)
System Bus
2.048 Mb/s
8.192 Mb/s
Data Sheet