mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 175

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

Bit
12
10 Tx8KEN Transmit 8 KHz Enable. If one, the pin RxMF transmits a positive 8 KHz frame pulse synchronous
11
9
8
7
6
5
4
3
2
1
0
MFSEL
THDB3
RxBFE
CSToE
DSToE
Name
MFBE
SPND
RxDO
RxCO
T2OP
CLKE
INTA
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
T2o Polarity. If one, the TxCL pin will output a 2.048 MHz clock whose rising edge is in the center
of the transmitted PCM30 bit cell at the TPOS and TNEG transmit pins. This clock is equivalent to
the internal ST-BUS C2 clock. If zero, the TxCL pin will output a 2.048 MHz clock whose falling
edge is in the center of the transmitted PCM30 bit cell at the TPOS and TNEG transmit pins. This
clock is equivalent to the internal ST-BUS C2 clock.
Transmit Multiframe Boundary Enable. If one, the TxMF pin will be enabled. If zero, the TxMF
pin will be disabled. See the TxMF pin description.
with the serial data stream transmit on TPOS/TNEG. If zero, the pin RxMF transmits a negative
frame pulse synchronous with the multiframe boundary of data coming out of DSTo.
Suspend Interrupts. If zero, the selected framers contribution to the IRQ pin output will be a high
impedance state, but all interrupt status registers will continue to be updated. If one, the selected
framers contribution to the IRQ output will be normal operation.
Interrupt Acknowledge. If zero, all interrupt and latched status registers are cleared and the
selected framers contribution to the IRQ pin output will be a high impedance state. If one, all
interrupt status registers and the selected framers contribution to the IRQ output will be normal
operation.
Clock Edge. If one then the NRZ data (RPOS/RNEG) is sampled on the rising edge of EXCLi and
transmitted on the falling edge of EXCLi. This selection is only applicable in NRZ mode.
THDB3 (High Density Bipolar 3) Encoding. If zero, HDB3 encoding is enabled in the transmit
direction. If one, AMI (Alternate Mark Inversion) signal without HDB3 encoding is enabled in the
transmit direction.
Receive Basic Frame Enable. If one, the RxBF pin operates normally. If zero, the RxBF pin is low.
Receive DSTo All Ones. If one, the DSTo pin operates normally. If zero, all timeslots (0-31) of
DSTo are set to one.
Receive CSTo All Ones. If one, the CSTo pin operates normally. If zero, all timeslots (0-31) of
CSTo are set to one.
Output CSTo Enable. If one, the CSTo pin operates normally. If zero, CSTo will be at high
impedance. In 8.192 Mbit/s mode all CSToE for all framers have to be 0 to obtain high impedance.
Output DSTo Enable. If one, the DSTo pin operates normally. If zero, DSTo will be at high
impedance.
Multiframe Select. This bit determines which receive multiframe signal (CRC-4 or signaling) the
frame pulse at the RxMF pin is aligned with. If zero, the frame pulse at the RxMF pin is aligned with
the receive channel associated signaling (CAS) multiframe; if one, the receive CRC-4 multiframe.
See Figures 55 & 58.
Table 144 - Interrupts and I/O Control Register (R/W Address Y02) (E1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
175
Data Sheet