mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 178

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-12
11-7
5-3
Bit
6
2
1
0
HPAYSEL
HCH4-0
TS31E
TS16E
TS15E
Name
(0)
(0)
(0)
(0)
(0)
#
#
Table 148 - HDLC & CCS ST-BUS Control Register (R/W Address Y06) (E1)
not used.
HDLC Channel 4-0. This 5 bit number specifies the channel time HDLC will be attached to
if enabled. Channel 1 is the first channel in the frame. Channel 31 is the last channel
available in a E1 frame. If enabled in a channel, HDLC data will be substituted for data from
DSTi on the transmit side. Receive data is extracted from the incoming line data before the
elastic buffer and decoded by the HDLC receiver. This bits are relevant if HPAYSEL is set.
HDLC Payload Select. Set this bit to 1 to attach HDLC0 to a payload timeslot, if zero it is
attached to the Facility data link in Timeslot 0 in accordance with selections in Y08.
not used
Time Slot 31 CST Enable. If one, the transmit PCM30 link timeslot 31 data will be sourced
from a CSTi timeslot as selected by control bits 31C4 to 31C0 of register address Y07. And,
the receive PCM30 link timeslot 31 data will be sourced to both DSTo timeslot 31 and to the
above selected CSTo timeslot. This feature is used to link PCM30 CCS data to an external
HDLC device through the CSTo and CSTi pins. If zero, the transmit PCM30 link timeslot 31
data will be sourced from DSTi timeslot 31. And, the receive PCM30 link timeslot 31 data
will be sourced to DSTo timeslot 31 only.
CCS (CSIG =1 of register address Y03) must be selected for these operations to be valid.
Time Slot 16 CST Enable. If one, the transmit PCM30 link timeslot 16 data will be sourced
from a CSTi timeslot as selected by control bits 16C4 to 16C0 of register address Y07. And,
the receive PCM30 link timeslot 16 data will be sourced to both DSTo timeslot 16 and to the
above selected CSTo timeslot. This feature is used to link PCM30 CCS data to an external
HDLC device through the CSTo and CSTi pins. If zero, the transmit PCM30 link timeslot 16
data will be sourced from DSTi timeslot 16. And, the receive PCM30 link timeslot 16 data
will be sourced to DSTo timeslot 16 only.
CCS (CSIG=1 of register address Y03) must be selected for these operations to be valid.
Time Slot 15 CST Enable. If one, the transmit PCM30 link timeslot 15 data will be sourced
from a CSTi timeslot as selected by control bits 15C4 to 15C0 of register address Y07. And,
the receive PCM30 link timeslot 15 data will be sourced to both DSTo timeslot 15 and to the
above selected CSTo timeslot. This feature is used to link PCM30 CCS data to an external
HDLC device through the CSTo and CSTi pins. If zero, the transmit PCM30 link timeslot 15
data will be sourced from DSTi timeslot 15. And, the receive PCM30 link timeslot 15 data
will be sourced to DSTo timeslot 15 only.
CCS (CSIG=1 of register address Y03) must be selected for these operations to be valid.
Zarlink Semiconductor Inc.
MT9072
Functional Description
178
Data Sheet