mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 180

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

4-2
Bit
15
14
13
14
13
10
9
8
7
6
5
Sa4SS
Sa5SS
Sa6SS
Sa7SS
Sa8SS
Name
(00)
(00)
(00)
(00)
(00)
#
#
not used.
Sa4 Source Select. These 2 bits determine the source of the transmit Sa4 bits in timeslot 0 of
NFAS frames.
Note the received Sa4 bits are always available in the RX National Data Bit Buffer (YC0) and
timeslot 0 on the DSTo pin.
Sa5 Source Select. These 2 bits determine the source of the transmit Sa5 bits in timeslot 0 of
NFAS frames.
Note the received Sa5 bits are always available in the RX National Data Bit Buffer (YC1) and
timeslot 0 on the DSTo pin.
Sa6 Source Select. These 2 bits determine the source of the transmit Sa6 bits in timeslot 0 of
NFAS frames.
Note the received Sa6 bits are always available in the RX National Data Bit Buffer (YC2) and
timeslot 0 on the DSTo pin.
Sa7 Source Select. These 2 bits determine the source of the transmit Sa7 bits in timeslot 0 of
NFAS frames.
Note the received Sa7 bits are always available in the RX National Data Bit Buffer (YC3) and
timeslot 0 on the DSTo pin.
Sa8 Source Select. These 2 bits determine the source of the transmit Sa8 bits in timeslot 0 of
NFAS frames.
Note the received Sa8 bits are always available to the RX National Data Bit Buffer (YC4) and
timeslot 0 on the DSto pin.
not used.
Table 150 - DataLink Control Register (R/W Address Y08) (E1)
Select Bits:
Select Bits:
Select Bits:
Select Bits:
Select Bits: Sa5 Source
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Sa4 Source
Transmit National Data Register (YB0)
TxDL pin (received Sa4 bits are sent to the RxDL pin)
DSTi pin (ST-BUS Channel 0, Bit 4 in NFAS frames)
HDLC (Transmit and Receive Sa4 bits)
Transmit National Data Register (YB1)
TxDL pin (received Sa5 bits are sent to the RxDL pin)
DSTi pin (ST-BUS Channel 0, Bit 3 in NFAS frames)
HDLC (Transmit and Receive Sa5 bits)
Sa6 Source
Transmit National Data Register (YB2)
TxDL pin (received Sa6 bits are sent to the RxDL pin)
DSTi pin (ST-BUS Channel 0, bit 2 in NFAS frames)
HDLC (Transmit and Receive Sa6 bits)
Sa7 Source
Transmit National Data Register (YB3)
TxDL pin (received Sa7 bits are sent to the RxDL pin)
DSTi pin (ST-BUS Channel 0, Bit 1 in NFAS frames)
HDLC (Transmit and Receive Sa7 bits)
Sa8 Source
Transmit National Data Register (YB4)
TxDL pin (received Sa8 bits are sent to the RxDL pin)
DSTi pin (ST-BUS Channel 0, Bit 1 in NFAS frames)
HDLC (Transmit and Receive Sa8 bits)
Zarlink Semiconductor Inc.
MT9072
Functional Description
180
Data Sheet