mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 192

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

17.2.5
Tables 173 to 181 describe the bit functions of each of the Latched Status Registers in the MT9072 in E1 mode.
Each register is repeated for each of the 8 framers. Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer 2
with Y=2 and so on up to Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB)
A11-A8). All latched status registers will be reset in the inactive state upon reset.
Table 169 - Sync, CRC-4 Remote, Alarms, MAS and Phase Latched Status Register (Address Y24) (E1)
Bit
15-9
15
14
13
Bit
8
7
6
5
4
3
2
1
0
RCRCRL Remote CRC-4 and RAI Latch. When the RCRCR status bit (register address Y10) toggles
Latched Status Registers (Y2X) Bit Functions
RSLPL
Name
#######
TXunder
EOPDL
EOPRL
TEOPL
RxOvfL
Name
#
TXFL
RxffL
GAL
FAL
not used.
from zero to one, this status bit is latched to one. This bit is cleared when either this register,
or the interrupt status register (register address Y34) is read.
Receive Slip Latch. When the RSLP status bit (register address Y13) toggles from zero to
one, or from one to zero, this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y34) is read.
not used.
Go Ahead received Latch.Indicates a go-ahead pattern (01111111) was detected by the
HDLC receiver. This bit is reset after a read.
End of Packet Data Latch.This bit is set when an end of packet (EOP) byte was written
into the RX FIFO by the HDLC receiver. This can be in the form of a flag, an abort
sequence or as an invalid packet. This bit is reset after a read.
Transmit End of Packet Latch.This bit is set when the transmitter has finished sending
the closing flag of a packet or after a packet has been aborted. This bit is reset after read.
End of Packet received latch.This bit is set when the byte about to be read from the RX
FIFO is the last byte of the packet. It is also set if the Rx FIFO is read and there is no data
in it. This bit is reset after a read.
Transmit Fifo Low Latch.This bit is set when the Tx FIFO is emptied below the selected
low threshold level. This bit is reset after a read.
Framer Abort Latch. This bit (FA) is set when a frame abort is received during packet
reception. It must be received after a minimum number of bits have been received (26)
otherwise it is ignored.
Txunder Latch.This bit is set for a TX FIFO underrun indication. If high it Indicates that a
read by the transmitter was attempted on an empty Tx FIFO. This bit is reset after a read.
Receive Fifo Full Latch.This bit is set when the Rx FIFO is filled above the selected full
threshold level. This bit is reset after a read.
Receive Overflow Latch.Indicates that the 32 byte RX FIFO overflowed (i.e., an attempt
to write to a 32 byte full RX FIFO). The HDLC will always disable the receiver once the
receive overflow has been detected. The receiver will be re-enabled upon detection of the
next flag, but will overflow again unless the RX FIFO is read. This bit is reset after a read.
Table 168 - HDLC Status Latch(Y23) (E1)
Zarlink Semiconductor Inc.
MT9072
Functional Description
192
Functional Description
Data Sheet